{"id":"https://openalex.org/W2054866332","doi":"https://doi.org/10.1109/patmos.2013.6662157","title":"Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design","display_name":"Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2054866332","doi":"https://doi.org/10.1109/patmos.2013.6662157","mag":"2054866332"},"language":"en","primary_location":{"id":"doi:10.1109/patmos.2013.6662157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2013.6662157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007431419","display_name":"Joakim Urdahl","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Joakim Urdahl","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002670917","display_name":"Shrinidhi Udupi","orcid":"https://orcid.org/0000-0002-3683-0888"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Shrinidhi Udupi","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047920654","display_name":"Dominik Stoffel","orcid":"https://orcid.org/0000-0002-8180-9738"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dominik Stoffel","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066184879","display_name":"Wolfgang Kunz","orcid":"https://orcid.org/0000-0002-6612-2946"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Kunz","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Kaiserslautern, Kaiserslautern, Germany]","institution_ids":["https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5007431419"],"corresponding_institution_ids":["https://openalex.org/I153267046"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11766807,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":null,"first_page":"67","last_page":"74"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.800438642501831},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.678501307964325},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.6042338013648987},{"id":"https://openalex.org/keywords/semantics","display_name":"Semantics (computer science)","score":0.55640709400177},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5396192073822021},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4991617202758789},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.47870731353759766},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.46993595361709595},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.45151519775390625},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4507959187030792},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.44507771730422974},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4344596564769745},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4216885566711426},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.40103864669799805},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34270408749580383},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3418736457824707},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.2760098874568939},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.18901944160461426},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17645084857940674},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09335169196128845}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.800438642501831},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.678501307964325},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.6042338013648987},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.55640709400177},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5396192073822021},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4991617202758789},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.47870731353759766},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.46993595361709595},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.45151519775390625},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4507959187030792},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.44507771730422974},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4344596564769745},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4216885566711426},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40103864669799805},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34270408749580383},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3418736457824707},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2760098874568939},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.18901944160461426},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17645084857940674},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09335169196128845},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/patmos.2013.6662157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2013.6662157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1509215027","https://openalex.org/W1968029379","https://openalex.org/W2057693164","https://openalex.org/W2098376757","https://openalex.org/W2122890990","https://openalex.org/W2165097265","https://openalex.org/W2170677925","https://openalex.org/W2402665206","https://openalex.org/W2471380925","https://openalex.org/W3150683616","https://openalex.org/W6674570594","https://openalex.org/W6713411876"],"related_works":["https://openalex.org/W2543290882","https://openalex.org/W2156420848","https://openalex.org/W2269990635","https://openalex.org/W1528726807","https://openalex.org/W2187417806","https://openalex.org/W2159022270","https://openalex.org/W1603163876","https://openalex.org/W2133642747","https://openalex.org/W2054866332","https://openalex.org/W2172255834"],"abstract_inverted_index":{"This":[0],"paper":[1,27,78],"surveys":[2,79],"the":[3,23,36,45,54,61,74,101,118,129,144,153,158],"state-of-the-art":[4],"in":[5,66,91],"operation-based":[6],"property":[7],"checking":[8],"and":[9,44,86,142,149],"describes":[10],"how":[11],"this":[12,30,139],"technique":[13,31],"can":[14,32,111],"be":[15,71,112,135],"used":[16],"to":[17,34,70,82],"conceptualize":[18],"on":[19,73],"a":[20,80,92,104],"design":[21,42,94],"at":[22,107,117,128],"Register-Transfer-Level":[24],"(RTL).":[25],"The":[26,58,77],"argues":[28],"that":[29,100,137],"contribute":[33],"closing":[35],"semantic":[37],"gap":[38],"between":[39,146],"system":[40,119],"level":[41,110,120],"descriptions":[43],"RTL":[46],"and,":[47],"thus,":[48],"opens":[49],"new":[50],"possibilities":[51],"for":[52,114,124],"solving":[53],"power":[55,126],"closure":[56],"problem.":[57],"semantics":[59],"of":[60,68,103,157],"high-level":[62],"model":[63],"are":[64,152],"defined":[65],"terms":[67],"properties":[69],"proven":[72],"concrete":[75],"RTL.":[76,130],"methodology":[81],"create":[83],"sound":[84],"abstractions":[85],"elaborates":[87],"their":[88],"possible":[89],"role":[90],"power-aware":[93],"flow.":[95],"Specifically,":[96],"it":[97],"is":[98],"demonstrated":[99],"availability":[102],"formal":[105],"specification":[106],"an":[108],"abstract":[109,160],"exploited":[113],"energy":[115,147],"estimations":[116],"as":[121,123],"well":[122],"deriving":[125],"optimizations":[127],"First":[131],"experimental":[132],"results":[133],"will":[134],"shown":[136],"demonstrate":[138],"optimization":[140],"potential":[141],"confirm":[143],"correlation":[145],"consumption":[148],"operations":[150],"which":[151],"basic":[154],"building":[155],"blocks":[156],"proposed":[159],"models.":[161]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}