{"id":"https://openalex.org/W4250565477","doi":"https://doi.org/10.1109/pact.2013.6618839","title":"PS-cache: An energy-efficient cache design for chip multiprocessors","display_name":"PS-cache: An energy-efficient cache design for chip multiprocessors","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W4250565477","doi":"https://doi.org/10.1109/pact.2013.6618839"},"language":"en","primary_location":{"id":"doi:10.1109/pact.2013.6618839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2013.6618839","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103499518","display_name":"Joan J. Valls","orcid":null},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Joan J. Valls","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073507304","display_name":"Alberto Ros","orcid":"https://orcid.org/0000-0001-5757-1064"},"institutions":[{"id":"https://openalex.org/I80180929","display_name":"Universidad de Murcia","ror":"https://ror.org/03p3aeb86","country_code":"ES","type":"education","lineage":["https://openalex.org/I80180929"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alberto Ros","raw_affiliation_strings":["Dept. de Ingenier\u00eda y Tecnolog\u00eda de Computadores, Universidad de Murcia, Spain"],"affiliations":[{"raw_affiliation_string":"Dept. de Ingenier\u00eda y Tecnolog\u00eda de Computadores, Universidad de Murcia, Spain","institution_ids":["https://openalex.org/I80180929"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Sahuquillo","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033867189","display_name":"Mar\u00eda E. G\u00f3mez","orcid":"https://orcid.org/0000-0003-1466-4118"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Maria E. Gomez","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5103499518"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":0.9456,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.78457281,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"407","last_page":"407"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8458808660507202},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7943277955055237},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6346793174743652},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5702032446861267},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5648695826530457},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.476046085357666},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.4702550172805786},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4467429220676422},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.42251208424568176},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.39599794149398804},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39475154876708984},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3205904960632324}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8458808660507202},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7943277955055237},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6346793174743652},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5702032446861267},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5648695826530457},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.476046085357666},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.4702550172805786},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4467429220676422},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.42251208424568176},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.39599794149398804},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39475154876708984},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3205904960632324},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pact.2013.6618839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2013.6618839","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2016521571","https://openalex.org/W2161381115"],"related_works":["https://openalex.org/W2363769136","https://openalex.org/W2133489088","https://openalex.org/W3085471909","https://openalex.org/W2031173804","https://openalex.org/W2114386333","https://openalex.org/W2734782074","https://openalex.org/W2115222420","https://openalex.org/W2126408955","https://openalex.org/W2098406302","https://openalex.org/W2148571123"],"abstract_inverted_index":{"As":[0],"silicon":[1],"resources":[2],"become":[3],"increasingly":[4],"abundant,":[5],"core":[6],"counts":[7],"grow":[8],"rapidly":[9],"in":[10,38,44],"successive":[11],"chip-multiprocessors":[12],"(CMP)":[13],"generations.":[14],"Parallel":[15],"workloads":[16,40],"represent":[17],"an":[18],"important":[19],"segment":[20],"for":[21],"current":[22],"and":[23,53],"future":[24],"CMPs":[25],"mainly":[26],"when":[27],"many-core":[28],"processors":[29],"are":[30],"considered.":[31],"Unlike":[32],"multiprogrammed":[33],"workloads,":[34],"the":[35,72],"accessed":[36,48,55],"blocks":[37],"these":[39],"can":[41],"be":[42],"classified":[43],"two":[45],"categories:":[46],"private,":[47],"only":[49,68],"by":[50,56],"one":[51],"core,":[52],"shared,":[54],"several":[57],"cores.":[58],"This":[59],"paper":[60],"takes":[61],"advantage":[62],"of":[63,71],"this":[64],"classification":[65],"to":[66],"access":[67],"a":[69],"subset":[70],"ways":[73],"on":[74],"each":[75],"L1":[76],"cache":[77],"access,":[78],"thus":[79],"reducing":[80],"dynamic":[81],"power":[82],"consumption.":[83]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
