{"id":"https://openalex.org/W4255264411","doi":"https://doi.org/10.1109/pact.2002.1106028","title":"Efficient interconnects for clustered microarchitectures","display_name":"Efficient interconnects for clustered microarchitectures","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4255264411","doi":"https://doi.org/10.1109/pact.2002.1106028"},"language":"en","primary_location":{"id":"doi:10.1109/pact.2002.1106028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2002.1106028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings.International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hdl.handle.net/2117/100592","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054367087","display_name":"Joan-Manuel Parcerisa","orcid":"https://orcid.org/0000-0001-5771-8118"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"J.-M. Parcerisa","raw_affiliation_strings":["Department Arquitectura de Computadors, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Department Arquitectura de Computadors, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Sahuquillo","raw_affiliation_strings":["Department Inform\u00e0tica de Sistemes i Computadors, Universitat Polit\u00e9cnica de Val\u00e9ncia, Spain"],"affiliations":[{"raw_affiliation_string":"Department Inform\u00e0tica de Sistemes i Computadors, Universitat Polit\u00e9cnica de Val\u00e9ncia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100733331","display_name":"Antonio Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-0009-0996"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Gonzalez","raw_affiliation_strings":["Intel Barcelona Research Center Intel Laboratories, Universitat Politecnica de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center Intel Laboratories, Universitat Politecnica de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040384183","display_name":"J. Duato","orcid":"https://orcid.org/0000-0002-7785-0607"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Duato","raw_affiliation_strings":["Department Arquitectura de Computadors, Universitat Polit\u00e9cnica de Val\u00e9ncia, Spain"],"affiliations":[{"raw_affiliation_string":"Department Arquitectura de Computadors, Universitat Polit\u00e9cnica de Val\u00e9ncia, Spain","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5054367087"],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":4.7186,"has_fulltext":false,"cited_by_count":25,"citation_normalized_percentile":{"value":0.95536883,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"291","last_page":"300"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8119181990623474},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7343186736106873},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.7115117311477661},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6790565252304077},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49172213673591614},{"id":"https://openalex.org/keywords/low-latency","display_name":"Low latency (capital markets)","score":0.46037063002586365},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4343945384025574},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4288051128387451},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3646184802055359},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.28286972641944885},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12105825543403625}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8119181990623474},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7343186736106873},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.7115117311477661},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6790565252304077},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49172213673591614},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.46037063002586365},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4343945384025574},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4288051128387451},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3646184802055359},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.28286972641944885},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12105825543403625}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/pact.2002.1106028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2002.1106028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings.International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"},{"id":"pmh:oai:upcommons.upc.edu:2117/100592","is_oa":true,"landing_page_url":"https://hdl.handle.net/2117/100592","pdf_url":null,"source":{"id":"https://openalex.org/S4210207057","display_name":"QRU Quaderns de Recerca en Urbanisme","issn_l":"2014-9689","issn":["2014-9689","2385-6777"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310322448","host_organization_name":"Q71272178","host_organization_lineage":["https://openalex.org/P4310322448"],"host_organization_lineage_names":["Q71272178"],"type":"journal"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"Conference report"}],"best_oa_location":{"id":"pmh:oai:upcommons.upc.edu:2117/100592","is_oa":true,"landing_page_url":"https://hdl.handle.net/2117/100592","pdf_url":null,"source":{"id":"https://openalex.org/S4210207057","display_name":"QRU Quaderns de Recerca en Urbanisme","issn_l":"2014-9689","issn":["2014-9689","2385-6777"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310322448","host_organization_name":"Q71272178","host_organization_lineage":["https://openalex.org/P4310322448"],"host_organization_lineage_names":["Q71272178"],"type":"journal"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"Conference report"},"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G2773299429","display_name":null,"funder_award_id":"TIC2001-0995-C02-01","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G3270740137","display_name":null,"funder_award_id":"FEDER fund","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G495392292","display_name":null,"funder_award_id":"FEDER","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1569032152","https://openalex.org/W1608995421","https://openalex.org/W1920053666","https://openalex.org/W2042008201","https://openalex.org/W2109054996","https://openalex.org/W2112833506","https://openalex.org/W2120062652","https://openalex.org/W2120734674","https://openalex.org/W2130838728","https://openalex.org/W2132148829","https://openalex.org/W2171825402","https://openalex.org/W2916411819","https://openalex.org/W3169463464","https://openalex.org/W4230929357","https://openalex.org/W4234104226","https://openalex.org/W4236258190","https://openalex.org/W4238644142","https://openalex.org/W4244330651","https://openalex.org/W4249006057","https://openalex.org/W4251468890","https://openalex.org/W4251852027","https://openalex.org/W4252737912","https://openalex.org/W6634019501","https://openalex.org/W6636146310","https://openalex.org/W6683563143","https://openalex.org/W6759615093","https://openalex.org/W6817363484"],"related_works":["https://openalex.org/W2520291760","https://openalex.org/W2391376741","https://openalex.org/W1976459683","https://openalex.org/W2393701163","https://openalex.org/W4232546846","https://openalex.org/W2011081932","https://openalex.org/W2387382509","https://openalex.org/W2116209852","https://openalex.org/W3205411230","https://openalex.org/W4286899009"],"abstract_inverted_index":{"Clustering":[0],"is":[1,58],"an":[2,69,125],"effective":[3,70],"microarchitectural":[4],"technique":[5],"for":[6,32,60,102],"reducing":[7],"the":[8,13,16,26,90,93],"impact":[9],"of":[10,19,28,38,92,124],"wire":[11],"delays,":[12],"complexity,":[14],"and":[15,43,75,117],"power":[17],"requirements":[18],"microprocessors.":[20],"In":[21,49],"this":[22],"work,":[23],"we":[24],"investigate":[25],"design":[27],"on-chip":[29],"interconnection":[30],"networks":[31],"clustered":[33,51],"microarchitectures.":[34],"This":[35],"new":[36],"class":[37],"interconnects":[39,66,110],"has":[40],"different":[41],"demands":[42],"characteristics":[44],"than":[45,83],"traditional":[46],"multiprocessor":[47],"networks.":[48],"a":[50,53,119],"microarchitecture,":[52],"low":[54],"inter-cluster":[55],"communication":[56],"latency":[57],"essential":[59],"high":[61,103],"performance.":[62,104],"We":[63,105],"propose":[64],"point-to-point":[65],"together":[67,95],"with":[68,96,114],"latency-aware":[71,97],"instruction":[72],"steering":[73,98],"scheme":[74],"show":[76,88,107],"that":[77,89,108,123],"they":[78],"achieve":[79,118],"much":[80],"better":[81],"performance":[82,120],"bus-based":[84],"interconnects.":[85],"The":[86],"results":[87],"connectivity":[91],"network":[94],"schemes":[99],"are":[100],"key":[101],"also":[106],"these":[109],"can":[111],"be":[112],"built":[113],"simple":[115],"hardware":[116],"close":[121],"to":[122],"idealized":[126],"contention-free":[127],"model.":[128]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}
