{"id":"https://openalex.org/W4242539338","doi":"https://doi.org/10.1109/pact.2002.1105970","title":"Increasing and detecting memory address congruence","display_name":"Increasing and detecting memory address congruence","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W4242539338","doi":"https://doi.org/10.1109/pact.2002.1105970"},"language":"en","primary_location":{"id":"doi:10.1109/pact.2002.1105970","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2002.1105970","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings.International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109221082","display_name":"S. Larsen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Larsen","raw_affiliation_strings":["MIT Laboratory for Computer Science, Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MIT Laboratory for Computer Science, Cambridge, MA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004286577","display_name":"Emmett Witchel","orcid":"https://orcid.org/0000-0002-1391-2880"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"E. Witchel","raw_affiliation_strings":["MIT Laboratory for Computer Science, Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MIT Laboratory for Computer Science, Cambridge, MA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046791216","display_name":"Saman Amarasinghe","orcid":"https://orcid.org/0000-0002-7231-7643"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Amarasinghe","raw_affiliation_strings":["MIT Laboratory for Computer Science, Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MIT Laboratory for Computer Science, Cambridge, MA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.0264,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.91890141,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"18","last_page":"29"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.866705596446991},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7473758459091187},{"id":"https://openalex.org/keywords/congruence","display_name":"Congruence (geometry)","score":0.6712767481803894},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6362963914871216},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5455637574195862},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.5095294117927551},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4985170364379883},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.46539151668548584},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.4453337788581848},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.4411277174949646},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.30002325773239136}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.866705596446991},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7473758459091187},{"id":"https://openalex.org/C132074034","wikidata":"https://www.wikidata.org/wiki/Q154210","display_name":"Congruence (geometry)","level":2,"score":0.6712767481803894},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6362963914871216},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5455637574195862},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.5095294117927551},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4985170364379883},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.46539151668548584},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.4453337788581848},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.4411277174949646},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.30002325773239136},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pact.2002.1105970","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pact.2002.1105970","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings.International Conference on Parallel Architectures and Compilation Techniques","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1534476433","https://openalex.org/W1816828244","https://openalex.org/W2010418442","https://openalex.org/W2038198320","https://openalex.org/W2040167141","https://openalex.org/W2042264308","https://openalex.org/W2111394443","https://openalex.org/W2117285153","https://openalex.org/W2137329733","https://openalex.org/W2167651816","https://openalex.org/W2171825402","https://openalex.org/W2249794205","https://openalex.org/W2752885492","https://openalex.org/W4232446824","https://openalex.org/W4236258190","https://openalex.org/W4240046008","https://openalex.org/W4256507744","https://openalex.org/W6632169842","https://openalex.org/W6677504465","https://openalex.org/W6680226504","https://openalex.org/W6691355889","https://openalex.org/W6817363484"],"related_works":["https://openalex.org/W1542435702","https://openalex.org/W2889415077","https://openalex.org/W2137300667","https://openalex.org/W4251068092","https://openalex.org/W2097395075","https://openalex.org/W2901114907","https://openalex.org/W4390073573","https://openalex.org/W2016937272","https://openalex.org/W2142272306","https://openalex.org/W2098901171"],"abstract_inverted_index":{"A":[0],"static":[1],"memory":[2,11,49,100],"reference":[3],"exhibits":[4],"a":[5,48,54,74,92,121,131,140,146,162],"unique":[6],"property":[7],"when":[8],"its":[9],"dynamic":[10,45],"addresses":[12,46],"are":[13,88,103,155],"congruent":[14,99],"with":[15],"respect":[16],"to":[17,90,106,145,157],"some":[18],"non-trivial":[19],"modulus.":[20],"Extraction":[21],"of":[22,31,47,98,109,123,139,148],"this":[23,35,59],"congruence":[24,42,126],"information":[25,127],"at":[26],"compile-time":[27],"enables":[28],"new":[29],"classes":[30],"program":[32],"optimization.":[33],"In":[34],"paper,":[36],"we":[37,134,154],"present":[38],"methods":[39],"for":[40,57],"forcing":[41],"among":[43],"the":[44,96,137,151],"reference.":[50],"We":[51,102],"also":[52],"introduce":[53,69],"compiler":[55,133],"algorithm":[56],"detecting":[58],"property.":[60],"Our":[61],"transformations":[62,87],"do":[63],"not":[64],"require":[65],"interprocedural":[66],"analysis":[67],"and":[68],"almost":[70],"no":[71],"overhead.":[72],"As":[73],"result,":[75],"they":[76],"can":[77,135],"be":[78],"incorporated":[79,129],"into":[80,130],"real":[81],"compilation":[82],"systems.":[83],"On":[84],"average,":[85],"our":[86],"able":[89,105,156],"achieve":[91],"five-fold":[93],"increase":[94,136],"in":[95,116,120,161],"number":[97],"operations.":[101],"then":[104],"detect":[107],"95%":[108],"these":[110],"references.":[111],"This":[112],"success":[113],"is":[114,128],"invaluable":[115],"providing":[117],"performance":[118,138],"gains":[119],"variety":[122],"areas.":[124],"When":[125],"vectorizing":[132],"G4":[141],"AltiVec":[142],"processor":[143],"up":[144],"factor":[147],"two.":[149],"Using":[150],"same":[152],"methods,":[153],"reduce":[158],"energy":[159],"consumption":[160],"data":[163],"cache":[164],"by":[165],"as":[166,168],"much":[167],"35%.":[169]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-08T01:25:22.217667","created_date":"2025-10-10T00:00:00"}