{"id":"https://openalex.org/W2771911737","doi":"https://doi.org/10.1109/pacrim.2017.8121918","title":"A mechanistic model of memory level parallelism fed with cache miss rates","display_name":"A mechanistic model of memory level parallelism fed with cache miss rates","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2771911737","doi":"https://doi.org/10.1109/pacrim.2017.8121918","mag":"2771911737"},"language":"en","primary_location":{"id":"doi:10.1109/pacrim.2017.8121918","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pacrim.2017.8121918","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102002663","display_name":"Qin Wang","orcid":"https://orcid.org/0000-0003-1521-3167"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Qin Wang","raw_affiliation_strings":["National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046533774","display_name":"Kecheng Ji","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kecheng Ji","raw_affiliation_strings":["National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078395317","display_name":"Ming Ling","orcid":"https://orcid.org/0000-0002-8866-7189"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ming Ling","raw_affiliation_strings":["National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101499715","display_name":"Longxing Shi","orcid":"https://orcid.org/0000-0002-0629-7154"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Longxing Shi","raw_affiliation_strings":["National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102002663"],"corresponding_institution_ids":["https://openalex.org/I76569877"],"apc_list":null,"apc_paid":null,"fwci":0.9013,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.76044767,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"39","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8796956539154053},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7748335599899292},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7396401166915894},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5658767819404602},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.49417904019355774},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4893002212047577},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.48182693123817444},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.4587843716144562},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.45787426829338074},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4444279670715332}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8796956539154053},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7748335599899292},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7396401166915894},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5658767819404602},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.49417904019355774},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4893002212047577},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.48182693123817444},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.4587843716144562},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.45787426829338074},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4444279670715332}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/pacrim.2017.8121918","is_oa":false,"landing_page_url":"https://doi.org/10.1109/pacrim.2017.8121918","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1522250664","https://openalex.org/W1821004526","https://openalex.org/W1965682443","https://openalex.org/W1972541532","https://openalex.org/W1976773142","https://openalex.org/W1981735283","https://openalex.org/W1986465830","https://openalex.org/W1986491730","https://openalex.org/W1986825865","https://openalex.org/W2019155735","https://openalex.org/W2040342412","https://openalex.org/W2052801483","https://openalex.org/W2060983019","https://openalex.org/W2075496654","https://openalex.org/W2097197938","https://openalex.org/W2127637835","https://openalex.org/W2143285027","https://openalex.org/W2145021036","https://openalex.org/W2147657366","https://openalex.org/W2273849591","https://openalex.org/W2292073965","https://openalex.org/W2613067490","https://openalex.org/W3146396127","https://openalex.org/W4236833104","https://openalex.org/W4238549726","https://openalex.org/W4246626299","https://openalex.org/W4251280768","https://openalex.org/W4255807648","https://openalex.org/W6631155369"],"related_works":["https://openalex.org/W2734782074","https://openalex.org/W2114386333","https://openalex.org/W2133489088","https://openalex.org/W2098406302","https://openalex.org/W2363769136","https://openalex.org/W2116323004","https://openalex.org/W4252570104","https://openalex.org/W2031173804","https://openalex.org/W2217292995","https://openalex.org/W2541463506"],"abstract_inverted_index":{"Non-blocking":[0],"caches,":[1],"which":[2,30,97],"are":[3,115],"commonly":[4],"utilized":[5],"in":[6],"modern":[7],"out-of-order":[8],"processors,":[9],"could":[10],"handle":[11],"multiple":[12],"outstanding":[13],"memory":[14,36,94],"requests":[15,37],"simultaneously":[16],"to":[17,32,50,65,125,161],"reduce":[18],"the":[19,33,61,74,119,130,141,148,162],"penalties":[20],"of":[21,35,76,93,121],"long":[22],"latency":[23],"cache":[24,52,77,83,149],"misses.":[25],"Memory":[26],"level":[27,95],"parallelism":[28],"(MLP),":[29],"refers":[31],"number":[34],"concurrently":[38],"held":[39],"by":[40],"Miss":[41],"Status":[42],"Handling":[43],"Registers":[44],"(MSHRs),":[45],"is":[46,136,144],"an":[47],"indispensable":[48],"factor":[49],"estimate":[51],"performance.":[53],"To":[54],"achieve":[55],"MLP":[56],"efficiently,":[57],"previous":[58],"researches":[59],"oversimplified":[60],"factors":[62],"that":[63],"need":[64],"be":[66,154],"considered":[67],"when":[68],"constructing":[69],"analytical":[70],"models,":[71],"especially":[72],"for":[73,117],"influences":[75],"miss":[78,84],"rate.":[79],"By":[80],"quantifying":[81],"above":[82],"rate":[85],"effects,":[86],"this":[87],"paper":[88],"proposes":[89],"a":[90],"mechanistic":[91],"model":[92],"parallelism,":[96],"performs":[98],"more":[99],"accurate":[100],"than":[101,138],"existing":[102],"works.":[103],"15":[104],"benchmarks,":[105],"chosen":[106],"from":[107],"Mobybench":[108],"2.0,":[109],"Mibench":[110],"1.0":[111],"and":[112],"MediaBench":[113],"II,":[114],"adopted":[116],"evaluating":[118],"accuracy":[120],"our":[122],"model.":[123],"Compared":[124],"Gem5":[126,163],"cycle-accurate":[127,164],"simulation":[128],"results,":[129],"largest":[131],"root":[132],"mean":[133],"square":[134],"error":[135],"less":[137],"11%,":[139],"while":[140],"average":[142],"one":[143],"around":[145],"7%.":[146],"Meanwhile,":[147],"performance":[150],"forecasting":[151],"process":[152],"can":[153],"sped":[155],"up":[156],"about":[157],"38":[158],"times":[159],"compared":[160],"simulations.":[165]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}