{"id":"https://openalex.org/W7168237731","doi":"https://doi.org/10.1109/ojcas.2026.3713363","title":"An IEEE-754 FP32 Marsaglia\u2013Polar Gaussian RNG on FPGA With AES-CTR Uniform Feeder","display_name":"An IEEE-754 FP32 Marsaglia\u2013Polar Gaussian RNG on FPGA With AES-CTR Uniform Feeder","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7168237731","doi":"https://doi.org/10.1109/ojcas.2026.3713363"},"language":"en","primary_location":{"id":"doi:10.1109/ojcas.2026.3713363","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3713363","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/ojcas.2026.3713363","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5140667232","display_name":"Arnab Kumar Biswas","orcid":"https://orcid.org/0000-0002-3057-2478"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Arnab Kumar Biswas","raw_affiliation_strings":["Queen\u2019s University Belfast"],"raw_orcid":"https://orcid.org/0000-0002-3057-2478","affiliations":[{"raw_affiliation_string":"Queen\u2019s University Belfast","institution_ids":["https://openalex.org/I126231945"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5140667232"],"corresponding_institution_ids":["https://openalex.org/I126231945"],"apc_list":{"value":2075,"currency":"USD","value_usd":2075},"apc_paid":{"value":2075,"currency":"USD","value_usd":2075},"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.75184822,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":null,"first_page":"418","last_page":"433"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.2996000051498413,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.2996000051498413,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12131","display_name":"Wireless Signal Modulation Classification","score":0.1737000048160553,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.125,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4625999927520752},{"id":"https://openalex.org/keywords/polar","display_name":"Polar","score":0.4219000041484833},{"id":"https://openalex.org/keywords/gaussian","display_name":"Gaussian","score":0.40400001406669617},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.3077999949455261},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3070000112056732}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5697000026702881},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4625999927520752},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4596000015735626},{"id":"https://openalex.org/C29705727","wikidata":"https://www.wikidata.org/wiki/Q294562","display_name":"Polar","level":2,"score":0.4219000041484833},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41130000352859497},{"id":"https://openalex.org/C163716315","wikidata":"https://www.wikidata.org/wiki/Q901177","display_name":"Gaussian","level":2,"score":0.40400001406669617},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.37299999594688416},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.3077999949455261},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3070000112056732},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.2800000011920929},{"id":"https://openalex.org/C61326573","wikidata":"https://www.wikidata.org/wiki/Q1496376","display_name":"Gaussian process","level":3,"score":0.2768000066280365},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25769999623298645},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.25540000200271606}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/ojcas.2026.3713363","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3713363","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/83fb22cb-ef82-496e-ba0b-aca38f6dd5db","is_oa":false,"landing_page_url":"https://pure.qub.ac.uk/en/publications/83fb22cb-ef82-496e-ba0b-aca38f6dd5db","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Biswas, A K 2026, 'An IEEE - 754 FP32 Marsaglia \u2013 Polar Gaussian RNG on FPGA with AES-CTR Uniform Feeder', IEEE Open Journal of Circuits and Systems. https://doi.org/10.1109/OJCAS.2026.3713363","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:doaj.org/article:5907d9a2cbcb499c8157827c84cb94ab","is_oa":false,"landing_page_url":"https://doaj.org/article/5907d9a2cbcb499c8157827c84cb94ab","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Open Journal of Circuits and Systems, Vol 7, Pp 418-433 (2026)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/ojcas.2026.3713363","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3713363","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5349041868","display_name":"Centre for Secure Information Technologies (CSIT) - Phase 3","funder_award_id":"EP/X022323/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"We":[0,85],"present":[1],"a":[2,37,144],"standards-compliant":[3],"IEEE":[4,82],"754":[5,83],"FP32":[6],"Gaussian":[7,51,128],"random":[8],"number":[9],"generator":[10],"(GRNG)":[11],"for":[12,28,124],"FPGA":[13],"based":[14],"on":[15,74],"the":[16,46,50,97,147],"Marsaglia\u2013polar":[17],"method,":[18],"designed":[19],"to":[20,67,139,174],"deliver":[21],"verifiable":[22],"tails":[23],"and":[24,30,61,104,116,126,136,152,162],"reproducible":[25],"floating-point":[26],"semantics":[27],"scientific":[29],"security-relevant":[31],"workloads.":[32],"The":[33],"key":[34],"contribution":[35],"is":[36],"streaming,":[38],"tokenized":[39],"polar":[40],"architecture":[41],"that":[42],"(i)":[43],"cleanly":[44],"separates":[45],"uniform":[47],"feeder":[48],"from":[49],"transform":[52],"core":[53],"(AES\u2013CTR":[54],"by":[55,58],"default,":[56],"swappable":[57],"threat":[59],"model),":[60],"(ii)":[62],"uses":[63],"IEEE-field-based":[64],"accept\u2013reject":[65],"gating":[66],"avoid":[68],"invoking":[69],"expensive":[70],"{ln,\u00f7,":[71],"\u221a\u00b7}":[72],"stages":[73],"invalid":[75],"samples,":[76],"improving":[77],"pipeline":[78],"efficiency":[79],"while":[80],"preserving":[81],"behavior.":[84],"complement":[86],"empirical":[87],"ULP/relative-error":[88],"checks":[89],"with":[90,165],"an":[91,171],"explicit":[92],"conditioning-based":[93],"stability":[94],"analysis":[95],"of":[96],"ln(s)":[98],"\u2192":[99,101],"/s":[100],"\u221a\u00b7":[102],"chain":[103],"validate":[105],"statistical":[106],"fidelity":[107],"via":[108],"histograms,":[109],"Q\u2013Q":[110],"plots,":[111],"Kolmogorov\u2013Smirnov":[112],"distances,":[113],"independence":[114],"checks,":[115],"large-N":[117],"tail":[118],"stress":[119],"testing.":[120],"Application-level":[121],"evaluations":[122],"(BER-over-AWGN":[123],"BPSK":[125],"DP-style":[127],"noise":[129],"injection":[130],"in":[131],"ML)":[132],"include":[133],"software":[134],"baselines":[135],"confidence":[137],"bounds":[138],"demonstrate":[140],"system-level":[141],"fidelity.":[142],"On":[143],"Xilinx":[145],"Artix\u20137,":[146],"post-route":[148],"design":[149],"meets":[150],"400MHz":[151],"produces":[153],"two":[154],"samples":[155],"per":[156],"cycle":[157],"(800MS/s)":[158],"using":[159],"1535":[160],"LUTs":[161],"12":[163],"DSPs,":[164],"total":[166],"power":[167],"0.264W":[168],"(dynamic":[169],"0.132W);":[170],"ASIC-scaled":[172],"projection":[173],"22nm":[175],"provides":[176],"contextual":[177],"throughput":[178],"comparison.":[179]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2026-07-15T00:00:00"}