{"id":"https://openalex.org/W7128705813","doi":"https://doi.org/10.1109/ojcas.2026.3664009","title":"Analog Convolution Circuit System Implemented With Capacitor Array Superposition","display_name":"Analog Convolution Circuit System Implemented With Capacitor Array Superposition","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7128705813","doi":"https://doi.org/10.1109/ojcas.2026.3664009"},"language":"en","primary_location":{"id":"doi:10.1109/ojcas.2026.3664009","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3664009","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/ojcas.2026.3664009","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113808704","display_name":"Chung-Yi Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Yi Wang","raw_affiliation_strings":["Department of Microelectronics, National Yang Ming Chaio Tung University, East District, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0008-5507-3449","affiliations":[{"raw_affiliation_string":"Department of Microelectronics, National Yang Ming Chaio Tung University, East District, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125695851","display_name":"Hsieh","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ping-Hsuan Hsieh","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0000-0003-4244-3558","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5125694623","display_name":"Ping-Hsuan","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Zi-Cin Wang","raw_affiliation_strings":["Department of Microelectronics, National Yang Ming Chaio Tung University, East District, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, National Yang Ming Chaio Tung University, East District, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1750,"currency":"USD","value_usd":1750},"apc_paid":{"value":1750,"currency":"USD","value_usd":1750},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17521571,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":null,"first_page":"60","last_page":"68"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9097999930381775,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9097999930381775,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.01489999983459711,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.010900000110268593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.6705999970436096},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.6657999753952026},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.6083999872207642},{"id":"https://openalex.org/keywords/superposition-principle","display_name":"Superposition principle","score":0.5159000158309937},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.48649999499320984},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.4399999976158142},{"id":"https://openalex.org/keywords/analog-computer","display_name":"Analog computer","score":0.430400013923645},{"id":"https://openalex.org/keywords/mnist-database","display_name":"MNIST database","score":0.36629998683929443},{"id":"https://openalex.org/keywords/impulse-response","display_name":"Impulse response","score":0.33180001378059387}],"concepts":[{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.6705999970436096},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.6657999753952026},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6108999848365784},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.6083999872207642},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5946000218391418},{"id":"https://openalex.org/C27753989","wikidata":"https://www.wikidata.org/wiki/Q284885","display_name":"Superposition principle","level":2,"score":0.5159000158309937},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.48649999499320984},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.4399999976158142},{"id":"https://openalex.org/C90915687","wikidata":"https://www.wikidata.org/wiki/Q63759","display_name":"Analog computer","level":2,"score":0.430400013923645},{"id":"https://openalex.org/C190502265","wikidata":"https://www.wikidata.org/wiki/Q17069496","display_name":"MNIST database","level":3,"score":0.36629998683929443},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3521000146865845},{"id":"https://openalex.org/C72279823","wikidata":"https://www.wikidata.org/wiki/Q1139726","display_name":"Impulse response","level":2,"score":0.33180001378059387},{"id":"https://openalex.org/C2776639384","wikidata":"https://www.wikidata.org/wiki/Q840396","display_name":"Ideal (ethics)","level":2,"score":0.32440000772476196},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.3050999939441681},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3019999861717224},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.28790000081062317},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2874000072479248},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.28690001368522644},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2824999988079071},{"id":"https://openalex.org/C379707","wikidata":"https://www.wikidata.org/wiki/Q2328303","display_name":"Analog signal processing","level":4,"score":0.27880001068115234},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.2752000093460083},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2694000005722046},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.2662999927997589},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2624000012874603},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2621999979019165},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.25440001487731934},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.2533999979496002},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25049999356269836}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ojcas.2026.3664009","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3664009","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:cc732c41e30642a68579284f486116cd","is_oa":false,"landing_page_url":"https://doaj.org/article/cc732c41e30642a68579284f486116cd","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Open Journal of Circuits and Systems, Vol 7, Pp 60-68 (2026)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/ojcas.2026.3664009","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3664009","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G7360853992","display_name":null,"funder_award_id":"114-2222-E-A49-002-","funder_id":"https://openalex.org/F4320331164","funder_display_name":"National Science and Technology Council"}],"funders":[{"id":"https://openalex.org/F4320331164","display_name":"National Science and Technology Council","ror":"https://ror.org/00wnb9798"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,30],"architecture":[4,54],"for":[5,41],"analog":[6,94],"convolution":[7,16,95],"computing":[8,96],"based":[9],"on":[10,57],"fundamental":[11],"series-parallel":[12],"capacitor":[13],"configurations.":[14],"The":[15,52],"results":[17],"are":[18],"digitized":[19],"through":[20],"a":[21],"capacitance-difference-to-digital":[22],"converter":[23],"(CDDC),":[24],"enabling":[25],"efficient":[26],"analog-to-digital":[27],"conversion.":[28],"Furthermore,":[29],"offset":[31,64],"calibration":[32,65],"mechanism":[33],"is":[34],"incorporated":[35],"into":[36],"the":[37,46,58,67,76,80,91],"CDDC":[38],"to":[39,73,86],"compensate":[40],"offset-induced":[42],"errors,":[43],"thereby":[44],"preserving":[45],"accuracy":[47],"of":[48,75,93],"AI":[49],"model":[50],"inference.":[51],"proposed":[53,81],"was":[55],"evaluated":[56],"MNIST":[59],"and":[60],"EMNIST":[61],"datasets.":[62],"With":[63],"enabled,":[66],"system":[68,82],"achieved":[69],"classification":[70],"accuracies":[71],"comparable":[72],"those":[74],"ideal":[77],"model.":[78],"Therefore,":[79],"can":[83],"be":[84],"adapted":[85],"various":[87],"semiconductor":[88],"processes,":[89],"facilitating":[90],"realization":[92],"chips.":[97]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-02-13T00:00:00"}