{"id":"https://openalex.org/W7125600567","doi":"https://doi.org/10.1109/ojcas.2026.3656510","title":"A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask","display_name":"A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7125600567","doi":"https://doi.org/10.1109/ojcas.2026.3656510"},"language":"en","primary_location":{"id":"doi:10.1109/ojcas.2026.3656510","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3656510","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://doi.org/10.1109/ojcas.2026.3656510","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5123781265","display_name":"Jaewon Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Jaewon Shin","raw_affiliation_strings":["Graduate School of Engineering, University of Tokyo, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0009-0004-7460-5894","affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018400474","display_name":"M. Hamada","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Mototsugu Hamada","raw_affiliation_strings":["Graduate School of Engineering, University of Tokyo, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0002-0461-4208","affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5123736632","display_name":"Atsutake Kosuge","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsutake Kosuge","raw_affiliation_strings":["Graduate School of Engineering, University of Tokyo, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0002-3394-2227","affiliations":[{"raw_affiliation_string":"Graduate School of Engineering, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":1750,"currency":"USD","value_usd":1750},"apc_paid":{"value":1750,"currency":"USD","value_usd":1750},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09085164,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":null,"first_page":"11","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.5932000279426575,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.5932000279426575,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.03720000013709068,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.03280000016093254,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5339999794960022},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5116999745368958},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.489300012588501},{"id":"https://openalex.org/keywords/pooling","display_name":"Pooling","score":0.46950000524520874},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.44600000977516174},{"id":"https://openalex.org/keywords/inference","display_name":"Inference","score":0.43849998712539673},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.42500001192092896},{"id":"https://openalex.org/keywords/base","display_name":"Base (topology)","score":0.3686000108718872},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.35760000348091125},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.35740000009536743}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.777400016784668},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5758000016212463},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5339999794960022},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5116999745368958},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.489300012588501},{"id":"https://openalex.org/C70437156","wikidata":"https://www.wikidata.org/wiki/Q7228652","display_name":"Pooling","level":2,"score":0.46950000524520874},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.44600000977516174},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4456000030040741},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.43849998712539673},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.42500001192092896},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39649999141693115},{"id":"https://openalex.org/C42058472","wikidata":"https://www.wikidata.org/wiki/Q810214","display_name":"Base (topology)","level":2,"score":0.3686000108718872},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.35760000348091125},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.35740000009536743},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.35249999165534973},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.3488999903202057},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.34709998965263367},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.34290000796318054},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33709999918937683},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3118000030517578},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.3102000057697296},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.30889999866485596},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.29010000824928284},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.28769999742507935},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2874000072479248},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.28529998660087585},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.28209999203681946},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.2759000062942505},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2705000042915344},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.26910001039505005},{"id":"https://openalex.org/C14737013","wikidata":"https://www.wikidata.org/wiki/Q1319657","display_name":"Photomask","level":4,"score":0.2680000066757202},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.2646999955177307},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.26409998536109924},{"id":"https://openalex.org/C153180895","wikidata":"https://www.wikidata.org/wiki/Q7148389","display_name":"Pattern recognition (psychology)","level":2,"score":0.25540000200271606},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2538999915122986},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2517000138759613},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.25110000371932983}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ojcas.2026.3656510","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3656510","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:10718298b30e4948a96ef0dd97de90d4","is_oa":true,"landing_page_url":"https://doaj.org/article/10718298b30e4948a96ef0dd97de90d4","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Open Journal of Circuits and Systems, Vol 7, Pp 11-20 (2026)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1109/ojcas.2026.3656510","is_oa":true,"landing_page_url":"https://doi.org/10.1109/ojcas.2026.3656510","pdf_url":null,"source":{"id":"https://openalex.org/S4210192473","display_name":"IEEE Open Journal of Circuits and Systems","issn_l":"2644-1225","issn":["2644-1225"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Open Journal of Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6718853116035461,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G6491443495","display_name":"\u30c7\u30d0\u30a4\u30b9\u30fb\u30b7\u30b9\u30c6\u30e0\u5354\u8abf\u306b\u3088\u308b\u8d85\u4f4e\u96fb\u5727\u5e03\u7dda\u8ad6\u7406\u578bAI\u30d7\u30ed\u30bb\u30c3\u30b5","funder_award_id":"JPMJPR21B4","funder_id":"https://openalex.org/F4320334789","funder_display_name":"Japan Science and Technology Agency"}],"funders":[{"id":"https://openalex.org/F4320334789","display_name":"Japan Science and Technology Agency","ror":"https://ror.org/00097mb19"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2082480549","https://openalex.org/W2095409369","https://openalex.org/W2981185037","https://openalex.org/W3135060602","https://openalex.org/W3206624709","https://openalex.org/W4289597973","https://openalex.org/W4291653242","https://openalex.org/W4317951947","https://openalex.org/W4378530790","https://openalex.org/W4385192610","https://openalex.org/W4387949904","https://openalex.org/W4404101464","https://openalex.org/W4408183565"],"related_works":[],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,28,35,62,94,131,147],"via-programmable":[4],"DNN":[5],"processor":[6],"architecture,":[7],"the":[8,57,83,127],"Via-Programmable":[9],"Neuron":[10],"Array":[11],"(VPNA),":[12],"designed":[13],"for":[14,87,150],"low-NRE":[15],"and":[16,48,73,79,103,117,140,153],"low-power":[17],"AIoT":[18,109,155],"applications.":[19],"To":[20],"enable":[21],"shared":[22],"base-chip":[23],"layouts":[24],"across":[25,107],"diverse":[26],"workloads,":[27],"connectivity-aware":[29],"design":[30],"ensures":[31],"tile-to-tile":[32],"routing":[33],"under":[34,76],"column-wise":[36],"placement":[37],"rule.":[38],"A":[39,66],"6\u00d7":[40],"6":[41],"programmable-wire":[42],"structure":[43],"supports":[44,71],"task-specific":[45],"data":[46],"paths,":[47],"via-based":[49],"ternary-weight":[50],"mapping":[51],"allows":[52],"multiple":[53],"tasks":[54],"to":[55],"reuse":[56],"same":[58],"base":[59],"chip":[60],"with":[61,122],"single":[63],"via":[64],"mask.":[65],"unified":[67],"bit-serial":[68],"neuron":[69],"circuit":[70],"convolution":[72],"pooling":[74],"operations":[75],"both":[77],"neuron-serial":[78],"neuron-parallel":[80],"modes,":[81],"completing":[82],"functional":[84],"implementation":[85],"required":[86],"one-dimensional":[88],"time-series":[89],"DNNs.":[90],"Post-layout":[91],"evaluations":[92],"in":[93],"40":[95],"nm":[96],"CMOS":[97],"process":[98],"demonstrate":[99],"sub-milliwatt":[100],"power":[101],"consumption":[102],"sufficient":[104],"inference":[105],"accuracy":[106],"representative":[108],"tasks,":[110],"including":[111],"keyword":[112],"spotting,":[113],"ECG":[114],"arrhythmia":[115],"detection,":[116],"EEG":[118],"seizure":[119],"detection.":[120],"Compared":[121],"prior":[123],"FPGA-and":[124],"ASIC-based":[125],"accelerators,":[126],"proposed":[128],"architecture":[129],"achieves":[130],"better":[132],"trade-off":[133],"among":[134],"low":[135,137],"power,":[136],"NRE":[138],"cost,":[139],"task-level":[141],"flexibility,":[142],"highlighting":[143],"its":[144],"potential":[145],"as":[146],"scalable":[148],"foundation":[149],"future":[151],"ultra-low-NRE":[152],"field-programmable":[154],"processors.":[156]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2026-01-25T00:00:00"}