{"id":"https://openalex.org/W2909252661","doi":"https://doi.org/10.1109/nvmts.2018.8603116","title":"Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning","display_name":"Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2909252661","doi":"https://doi.org/10.1109/nvmts.2018.8603116","mag":"2909252661"},"language":"en","primary_location":{"id":"doi:10.1109/nvmts.2018.8603116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nvmts.2018.8603116","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Non-Volatile Memory Technology Symposium (NVMTS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032094524","display_name":"Qilin Zheng","orcid":"https://orcid.org/0000-0002-5593-1369"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qilin Zheng","raw_affiliation_strings":["Institute of Microelectronics, Peking University, Beijing, P.R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University, Beijing, P.R. China","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089981020","display_name":"Zongwei Wang","orcid":"https://orcid.org/0000-0001-6297-2700"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zongwei Wang","raw_affiliation_strings":["Institute of Microelectronics, Peking University, Beijing, P.R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University, Beijing, P.R. China","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046926193","display_name":"Jian Kang","orcid":"https://orcid.org/0000-0001-7669-035X"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Kang","raw_affiliation_strings":["Institute of Microelectronics, Peking University, Beijing, P.R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University, Beijing, P.R. China","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078861478","display_name":"Zhizhen Yu","orcid":"https://orcid.org/0000-0001-8295-6310"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhizhen Yu","raw_affiliation_strings":["Institute of Microelectronics, Peking University, Beijing, P.R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University, Beijing, P.R. China","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060554231","display_name":"Yimao Cai","orcid":"https://orcid.org/0000-0002-6854-8211"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yimao Cai","raw_affiliation_strings":["Institute of Microelectronics, Peking University, Beijing, P.R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University, Beijing, P.R. China","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111638577","display_name":"Jintong Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210135723","display_name":"Shanghai Institute of Technical Physics","ror":"https://ror.org/02txedb84","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210135723"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jintong Xu","raw_affiliation_strings":["Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai, P. R. China","institution_ids":["https://openalex.org/I4210135723","https://openalex.org/I19820366"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15518022,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mnist-database","display_name":"MNIST database","score":0.9187018871307373},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.8969318866729736},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8591568470001221},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.8247009515762329},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7401266694068909},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5144253373146057},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5018808841705322},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.45359179377555847},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4276329278945923},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4122955799102783},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3724784851074219},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3466983437538147},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33908647298812866},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2761732339859009},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26575803756713867},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.20865285396575928},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20061716437339783},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1545027494430542},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1291947364807129}],"concepts":[{"id":"https://openalex.org/C190502265","wikidata":"https://www.wikidata.org/wiki/Q17069496","display_name":"MNIST database","level":3,"score":0.9187018871307373},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.8969318866729736},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8591568470001221},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.8247009515762329},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7401266694068909},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5144253373146057},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5018808841705322},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.45359179377555847},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4276329278945923},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4122955799102783},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3724784851074219},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3466983437538147},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33908647298812866},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2761732339859009},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26575803756713867},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.20865285396575928},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20061716437339783},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1545027494430542},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1291947364807129},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nvmts.2018.8603116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nvmts.2018.8603116","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Non-Volatile Memory Technology Symposium (NVMTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2027342132","https://openalex.org/W2060150004","https://openalex.org/W2120557145","https://openalex.org/W2336860599","https://openalex.org/W2583536366","https://openalex.org/W2785346409","https://openalex.org/W2785988257","https://openalex.org/W6677793910","https://openalex.org/W6747701038","https://openalex.org/W6748707121"],"related_works":["https://openalex.org/W3005999147","https://openalex.org/W4386216112","https://openalex.org/W3176428941","https://openalex.org/W3089883684","https://openalex.org/W4232634182","https://openalex.org/W4301187613","https://openalex.org/W2923038022","https://openalex.org/W3008646524","https://openalex.org/W1636374761","https://openalex.org/W4385624997"],"abstract_inverted_index":{"Write":[0],"Variation":[1],"is":[2],"an":[3],"inevitable":[4],"non-ideal":[5],"effects":[6],"for":[7,58],"Resistive":[8],"Random":[9],"Access":[10],"Memory(ReRAM)":[11],"based":[12],"On-chip":[13],"Neural":[14],"Networks":[15],"training,":[16],"which":[17],"incurs":[18],"significant":[19],"accuracy":[20,41,51],"drops":[21],"and":[22,42],"affects":[23],"the":[24,44],"system":[25,45],"robustness.":[26],"In":[27],"this":[28],"paper,":[29],"we":[30],"have":[31],"proposed":[32],"a":[33,38],"Hierarchical":[34],"Crossbar(HC)":[35],"to":[36,47],"achieve":[37],"software":[39],"competitive":[40],"enhanced":[43,56],"robustness":[46],"random":[48],"effects.":[49],"The":[50],"on":[52],"MNIST":[53],"can":[54],"be":[55],"10%":[57],"2000":[59],"iterations":[60],"on-chip":[61],"fine-tuning":[62],"comparing":[63],"with":[64],"conventional":[65],"crossbar.":[66]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}