{"id":"https://openalex.org/W7140295826","doi":"https://doi.org/10.1109/nvmsa66678.2025.00016","title":"Application of Nonvolatile IP with MTJ to eFPGA","display_name":"Application of Nonvolatile IP with MTJ to eFPGA","publication_year":2025,"publication_date":"2025-08-20","ids":{"openalex":"https://openalex.org/W7140295826","doi":"https://doi.org/10.1109/nvmsa66678.2025.00016"},"language":null,"primary_location":{"id":"doi:10.1109/nvmsa66678.2025.00016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nvmsa66678.2025.00016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 14th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041270546","display_name":"Keizo Hiraga","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Keizo Hiraga","raw_affiliation_strings":["Sony Semiconductor Solutions Corporation,Atsugi,Japan"],"affiliations":[{"raw_affiliation_string":"Sony Semiconductor Solutions Corporation,Atsugi,Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130604002","display_name":"Kenshu Seto","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenshu Seto","raw_affiliation_strings":["Kumamoto University,Kumamoto,Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University,Kumamoto,Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5130626988","display_name":"Kazuhiro Bessho","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kazuhiro Bessho","raw_affiliation_strings":["Sony Semiconductor Solutions Corporation,Atsugi,Japan"],"affiliations":[{"raw_affiliation_string":"Sony Semiconductor Solutions Corporation,Atsugi,Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5130553000","display_name":"Masahiro Iida","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Iida","raw_affiliation_strings":["Kumamoto University,Kumamoto,Japan"],"affiliations":[{"raw_affiliation_string":"Kumamoto University,Kumamoto,Japan","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5041270546"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.80540484,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"48","last_page":"53"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.17749999463558197,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.17749999463558197,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.1193000003695488,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.08900000154972076,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.5978999733924866},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5684999823570251},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5450999736785889},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4778999984264374},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.42559999227523804},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.34610000252723694},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.3188000023365021},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.3089999854564667}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.65829998254776},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6039000153541565},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.5978999733924866},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5684999823570251},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5450999736785889},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4778999984264374},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.42559999227523804},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.34610000252723694},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.3188000023365021},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.3089999854564667},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3052000105381012},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29649999737739563},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.29319998621940613},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.287200003862381},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2802000045776367},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.27730000019073486},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.27410000562667847},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.27239999175071716},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.26840001344680786},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.2655999958515167},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.2639000117778778},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.2612999975681305},{"id":"https://openalex.org/C204323151","wikidata":"https://www.wikidata.org/wiki/Q905424","display_name":"Range (aeronautics)","level":2,"score":0.2590999901294708},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2547000050544739},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.2533999979496002}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nvmsa66678.2025.00016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nvmsa66678.2025.00016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 14th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2073801038","https://openalex.org/W2760836853","https://openalex.org/W2911464632","https://openalex.org/W2922071906","https://openalex.org/W3028321762","https://openalex.org/W4320015774","https://openalex.org/W4385209678","https://openalex.org/W4391236668","https://openalex.org/W4392208264","https://openalex.org/W4411207646"],"related_works":[],"abstract_inverted_index":{"In":[0,47,100,123,188],"embedded":[1,53],"real-time":[2],"systems,":[3],"which":[4],"are":[5,174],"important":[6],"infrastructure":[7],"in":[8,170],"modern":[9],"society,":[10],"fault-tolerant":[11],"design":[12],"is":[13,43,77,89,126],"essential":[14],"to":[15,20,65,92,94,128,144,162,168,178,208],"prevent":[16],"system":[17],"shutdowns":[18],"due":[19,143],"power":[21,42,67,141,186],"failures.":[22],"Previous":[23],"research":[24],"has":[25],"demonstrated":[26],"systems":[27,164],"using":[28,213],"non-volatile":[29,121,194],"technology,":[30],"but":[31],"measures":[32],"for":[33,80],"cases":[34],"where":[35],"complete":[36],"functionality":[37,59],"cannot":[38],"be":[39,160,197],"restored":[40,44],"after":[41],"were":[45],"insufficient.":[46],"this":[48,101,189],"study,":[49,102],"we":[50,103,191],"focus":[51,104],"on":[52,105],"FPGAs":[54],"(eFPGAs)":[55],"and":[56,116,148,183],"propose":[57],"a":[58,130,214],"recovery":[60],"mechanism":[61],"that":[62,111,165,173,193],"can":[63,112,166,196],"respond":[64,93],"unexpected":[66],"interruptions":[68],"by":[69],"making":[70],"them":[71],"non-volatile.":[72],"Although":[73],"traditional":[74],"hard":[75],"IP":[76,88],"the":[78,82,95,118,155],"mainstream":[79],"eFPGAs,":[81],"spread":[83],"of":[84,97,120,133,151,203],"more":[85],"flexible":[86],"soft":[87],"attracting":[90],"attention":[91],"evolution":[96],"performance":[98],"generations.":[99],"programmable":[106],"AND":[107],"element":[108],"(PAE)-based":[109],"eFPGAs":[110,195,210],"reduce":[113],"configuration":[114],"memory":[115],"realize":[117],"implementation":[119],"technology.":[122],"addition,":[124],"non-volatility":[125],"expected":[127],"provide":[129],"wide":[131],"range":[132],"benefits,":[134],"such":[135,180],"as":[136,181],"shorter":[137],"startup":[138],"times,":[139],"lower":[140],"consumption":[142],"reduced":[145],"data":[146,152],"transfer,":[147],"improved":[149],"security":[150],"management":[153],"within":[154],"chip.":[156],"Furthermore,":[157],"it":[158],"will":[159],"possible":[161],"build":[163],"continue":[167],"operate":[169],"harsh":[171],"environments":[172],"not":[175],"easily":[176],"accessible":[177],"humans,":[179],"space":[182],"inside":[184],"nuclear":[185],"plants.":[187],"paper,":[190],"show":[192],"realized":[198],"with":[199],"an":[200],"area":[201],"increase":[202],"about":[204],"1.5":[205],"times":[206],"compared":[207],"volatile":[209],"through":[211],"evaluation":[212],"40nm":[215],"MTJ/CMOS":[216],"process.":[217]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2026-03-26T00:00:00"}