{"id":"https://openalex.org/W1995365306","doi":"https://doi.org/10.1109/norchp.2012.6403129","title":"A light-weight statically scheduled network-on-chip","display_name":"A light-weight statically scheduled network-on-chip","publication_year":2012,"publication_date":"2012-11-01","ids":{"openalex":"https://openalex.org/W1995365306","doi":"https://doi.org/10.1109/norchp.2012.6403129","mag":"1995365306"},"language":"en","primary_location":{"id":"doi:10.1109/norchp.2012.6403129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchp.2012.6403129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NORCHIP 2012","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072194828","display_name":"Ronald B. Sorensen","orcid":"https://orcid.org/0000-0001-6539-4782"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"R. B. Sorensen","raw_affiliation_strings":["Department of Informatics and Mathematical Modeling, Technical University of Denmark, Denmark#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics and Mathematical Modeling, Technical University of Denmark, Denmark#TAB#","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083205602","display_name":"Martin Schoeberl","orcid":"https://orcid.org/0000-0003-2366-382X"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"M. Schoeberl","raw_affiliation_strings":["Department of Informatics and Mathematical Modeling, Technical University of Denmark","Department of Informatics and Mathematical Modeling, Technical University of Denmark, Denmark#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics and Mathematical Modeling, Technical University of Denmark","institution_ids":["https://openalex.org/I96673099"]},{"raw_affiliation_string":"Department of Informatics and Mathematical Modeling, Technical University of Denmark, Denmark#TAB#","institution_ids":["https://openalex.org/I96673099"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055051850","display_name":"Jens Spars\u00f8","orcid":"https://orcid.org/0000-0002-0961-9438"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"J. Sparso","raw_affiliation_strings":["Department of Informatics and Mathematical Modeling, Technical University of Denmark, Denmark#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics and Mathematical Modeling, Technical University of Denmark, Denmark#TAB#","institution_ids":["https://openalex.org/I96673099"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I96673099"],"apc_list":null,"apc_paid":null,"fwci":1.6977,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.83271754,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.7192156910896301},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7094431519508362},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7003377079963684},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6702694296836853},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6395375728607178},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6230882406234741},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5322079062461853},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5115221738815308},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5010743141174316},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.286514014005661},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2660204768180847},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09788712859153748}],"concepts":[{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.7192156910896301},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7094431519508362},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7003377079963684},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6702694296836853},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6395375728607178},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6230882406234741},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5322079062461853},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5115221738815308},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5010743141174316},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.286514014005661},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2660204768180847},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09788712859153748}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/norchp.2012.6403129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchp.2012.6403129","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NORCHIP 2012","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.303.3981","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.303.3981","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.jopdesign.com/doc/s4noceval.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:publications/f7aeee11-c9c9-4a2a-a2a3-3295da3b79db","is_oa":false,"landing_page_url":"https://orbit.dtu.dk/en/publications/f7aeee11-c9c9-4a2a-a2a3-3295da3b79db","pdf_url":null,"source":{"id":"https://openalex.org/S4306400705","display_name":"Technical University of Denmark, DTU Orbit (Technical University of Denmark, DTU)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I96673099","host_organization_name":"Technical University of Denmark","host_organization_lineage":["https://openalex.org/I96673099"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"S\u00f8rensen , R B , Schoeberl , M & Spars\u00f8 , J 2012 , A Light-Weight Statically Scheduled Network-on-Chip . in 2012 NORCHIP . IEEE , 2012 IEEE 30th NORCHIP Conference , Copenhagen , Denmark , 12/11/2012 . https://doi.org/10.1109/NORCHP.2012.6403129","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320338075","display_name":"Core Research for Evolutional Science and Technology","ror":"https://ror.org/00097mb19"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1946139549","https://openalex.org/W1970079160","https://openalex.org/W1999309919","https://openalex.org/W2012959791","https://openalex.org/W2021767866","https://openalex.org/W2088479706","https://openalex.org/W2119699246","https://openalex.org/W2119865827","https://openalex.org/W2125028861","https://openalex.org/W2131180102","https://openalex.org/W2141497161","https://openalex.org/W2157364933","https://openalex.org/W2168082067","https://openalex.org/W3144593894","https://openalex.org/W4237692873"],"related_works":["https://openalex.org/W3010619501","https://openalex.org/W2161995522","https://openalex.org/W2889326901","https://openalex.org/W2135981148","https://openalex.org/W2043881088","https://openalex.org/W2390899382","https://openalex.org/W2388672758","https://openalex.org/W2065289416","https://openalex.org/W2754086592","https://openalex.org/W2144357574"],"abstract_inverted_index":{"This":[0],"paper":[1],"investigates":[2],"how":[3],"a":[4,37,43,54],"light-weight,":[5],"statically":[6],"scheduled":[7],"network-on-chip":[8],"(NoC)":[9],"for":[10],"real-time":[11],"systems":[12],"can":[13],"be":[14],"designed":[15],"and":[16,29,35],"implemented.":[17],"The":[18,31],"NoC":[19,52],"provides":[20],"communication":[21],"channels":[22],"between":[23],"all":[24],"cores":[25],"with":[26,49],"equal":[27],"bandwidth":[28],"latency.":[30],"design":[32],"is":[33],"FPGA-friendly":[34],"consumes":[36],"minimum":[38],"of":[39],"resources.":[40],"We":[41],"implemented":[42],"64":[44],"core":[45],"16-bit":[46],"multiprocessor":[47],"connected":[48],"the":[50],"proposed":[51],"in":[53],"low-cost":[55],"FPGA.":[56]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}