{"id":"https://openalex.org/W2065072790","doi":"https://doi.org/10.1109/norchp.2012.6403113","title":"Novel SRAM bias control circuits for a low power L1 data cache","display_name":"Novel SRAM bias control circuits for a low power L1 data cache","publication_year":2012,"publication_date":"2012-11-01","ids":{"openalex":"https://openalex.org/W2065072790","doi":"https://doi.org/10.1109/norchp.2012.6403113","mag":"2065072790"},"language":"en","primary_location":{"id":"doi:10.1109/norchp.2012.6403113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchp.2012.6403113","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NORCHIP 2012","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044470095","display_name":"A. Seyedi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210164937","display_name":"Microsoft Research (United Kingdom)","ror":"https://ror.org/05k87vq12","country_code":"GB","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210164937"]},{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["GB","US"],"is_corresponding":true,"raw_author_name":"A. Seyedi","raw_affiliation_strings":["BSC-Microsoft Research Centre","BSC-Microsoft Res. Centre, Spain"],"affiliations":[{"raw_affiliation_string":"BSC-Microsoft Research Centre","institution_ids":["https://openalex.org/I4210164937"]},{"raw_affiliation_string":"BSC-Microsoft Res. Centre, Spain","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049697257","display_name":"Adri\u00e0 Armejach","orcid":"https://orcid.org/0000-0003-2869-668X"},"institutions":[{"id":"https://openalex.org/I4210164937","display_name":"Microsoft Research (United Kingdom)","ror":"https://ror.org/05k87vq12","country_code":"GB","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210164937"]},{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"A. Armejach","raw_affiliation_strings":["BSC-Microsoft Research Centre","BSC-Microsoft Res. Centre, Spain"],"affiliations":[{"raw_affiliation_string":"BSC-Microsoft Research Centre","institution_ids":["https://openalex.org/I4210164937"]},{"raw_affiliation_string":"BSC-Microsoft Res. Centre, Spain","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084390427","display_name":"Adri\u00e1n Cristal","orcid":"https://orcid.org/0000-0003-1277-9296"},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"funder","lineage":["https://openalex.org/I134820265"]},{"id":"https://openalex.org/I4210131846","display_name":"Artificial Intelligence Research Institute","ror":"https://ror.org/03c0ach84","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210131846"]},{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["ES","US"],"is_corresponding":false,"raw_author_name":"A. Cristal","raw_affiliation_strings":["IIIA - Artificial Intelligence Research Institute CSIC - Spanish National Research Council","BSC-Microsoft Res. Centre, Spain"],"affiliations":[{"raw_affiliation_string":"IIIA - Artificial Intelligence Research Institute CSIC - Spanish National Research Council","institution_ids":["https://openalex.org/I4210131846","https://openalex.org/I134820265"]},{"raw_affiliation_string":"BSC-Microsoft Res. Centre, Spain","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075162875","display_name":"Osman \u00dcnsal","orcid":"https://orcid.org/0000-0002-0544-9697"},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]},{"id":"https://openalex.org/I4210164937","display_name":"Microsoft Research (United Kingdom)","ror":"https://ror.org/05k87vq12","country_code":"GB","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210164937"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"O. S. Unsal","raw_affiliation_strings":["BSC-Microsoft Research Centre","BSC-Microsoft Res. Centre, Spain"],"affiliations":[{"raw_affiliation_string":"BSC-Microsoft Research Centre","institution_ids":["https://openalex.org/I4210164937"]},{"raw_affiliation_string":"BSC-Microsoft Res. Centre, Spain","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020844763","display_name":"Mateo Valero","orcid":"https://orcid.org/0000-0003-2917-2482"},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]},{"id":"https://openalex.org/I4210164937","display_name":"Microsoft Research (United Kingdom)","ror":"https://ror.org/05k87vq12","country_code":"GB","type":"company","lineage":["https://openalex.org/I1290206253","https://openalex.org/I4210164937"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"M. Valero","raw_affiliation_strings":["BSC-Microsoft Research Centre","BSC-Microsoft Res. Centre, Spain"],"affiliations":[{"raw_affiliation_string":"BSC-Microsoft Research Centre","institution_ids":["https://openalex.org/I4210164937"]},{"raw_affiliation_string":"BSC-Microsoft Res. Centre, Spain","institution_ids":["https://openalex.org/I1290206253"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5044470095"],"corresponding_institution_ids":["https://openalex.org/I1290206253","https://openalex.org/I4210164937"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.60313725,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7658034563064575},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.700980544090271},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6294183135032654},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5313713550567627},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5289779901504517},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4863291382789612},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4119139015674591},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3283863961696625},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3151717185974121},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26556396484375},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.20338362455368042},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18023937940597534}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7658034563064575},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.700980544090271},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6294183135032654},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5313713550567627},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5289779901504517},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4863291382789612},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4119139015674591},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3283863961696625},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3151717185974121},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26556396484375},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.20338362455368042},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18023937940597534}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchp.2012.6403113","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchp.2012.6403113","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"NORCHIP 2012","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9200000166893005,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1527183359","https://openalex.org/W1566916904","https://openalex.org/W1899658488","https://openalex.org/W1989069093","https://openalex.org/W2003874403","https://openalex.org/W2021030008","https://openalex.org/W2029479717","https://openalex.org/W2081297699","https://openalex.org/W2085458736","https://openalex.org/W2094662129","https://openalex.org/W2099661831","https://openalex.org/W2099911327","https://openalex.org/W2103126659","https://openalex.org/W2104491047","https://openalex.org/W2105377990","https://openalex.org/W2108911707","https://openalex.org/W2124651507","https://openalex.org/W2126357937","https://openalex.org/W2140219379","https://openalex.org/W2144927208","https://openalex.org/W2149097694","https://openalex.org/W2163654949","https://openalex.org/W2789228616","https://openalex.org/W4211249698","https://openalex.org/W4256652509","https://openalex.org/W6675036846","https://openalex.org/W6681602448"],"related_works":["https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W2186949690","https://openalex.org/W2167303720","https://openalex.org/W2154109900","https://openalex.org/W2497617944","https://openalex.org/W3019064768","https://openalex.org/W1563139915","https://openalex.org/W2109715593","https://openalex.org/W2061075966"],"abstract_inverted_index":{"This":[0,202],"paper":[1],"proposes":[2],"two":[3],"novel":[4],"bias":[5,54,75,144],"control":[6,145],"circuits":[7,22,146,181],"to":[8,32,72,86,98,147,182,197],"manage":[9],"the":[10,48,53,59,74,80,142,158,176,184,198,228],"power":[11,25,133],"consumption":[12,26,186],"of":[13,56,178,187,210],"inactive":[14],"cache":[15,113,153,160,191],"cells":[16],"in":[17],"data":[18,112,190],"retention":[19],"mode.":[20],"Both":[21],"have":[23],"lower":[24],"and":[27,51,77,135,154,156,169,214],"area":[28,208],"overheads":[29],"when":[30],"compared":[31,196],"previous":[33],"proposals.":[34],"The":[35,173],"first":[36],"proposed":[37,109,143,180],"circuit":[38,42,64,137],"(Dynamic":[39],"Bias":[40,62],"Control":[41,63],"or":[43,65],"DB-Control":[44],"circuit)":[45,67],"dynamically":[46],"tracks":[47],"reference":[49],"current":[50,128],"sets":[52],"voltage":[55],"cells,":[57],"while":[58],"second":[60],"(Self-Adjust":[61],"SAB-Control":[66,229],"has":[68,115,129],"a":[69,107,148,206],"self-adjust":[70],"property":[71],"set":[73],"voltages":[76],"also":[78,219],"alleviates":[79],"instability":[81,222],"problems":[82,223],"that":[83,114,121,221],"appear":[84],"due":[85],"noise":[87],"injection.":[88],"Although":[89],"any":[90],"SRAM":[91,151],"array":[92],"can":[93],"benefit":[94],"from":[95],"these":[96],"circuits,":[97],"show":[99,220],"their":[100],"usefulness,":[101],"we":[102,140],"frame":[103],"our":[104,179],"study":[105],"on":[106,132,136,194],"recently":[108],"dual-versioning":[110,150],"L1":[111,189],"been":[116],"designed":[117],"for":[118],"chip":[119],"multi-processors":[120],"implement":[122],"optimistic":[123],"concurrency":[124],"proposals,":[125],"where":[126],"leakage":[127],"more":[130],"effect":[131],"dissipation":[134],"instability.":[138],"Therefore,":[139],"add":[141],"32KB":[149],"(dvSRAM)":[152],"simulate":[155],"optimize":[157],"entire":[159],"with":[161,205],"45-nm":[162],"CMOS":[163],"technology":[164],"at":[165],"2GHz":[166],"processor":[167],"frequency":[168],"1V":[170],"supply":[171],"voltage.":[172],"simulations":[174],"demonstrate":[175],"effectiveness":[177],"reduce":[183],"energy":[185],"dvSRAM":[188,200],"by":[192,226],"35.8%":[193],"average":[195],"typical":[199],"cache.":[201],"is":[203],"achieved":[204],"modest":[207],"increase":[209],"1.6%":[211],"per":[212],"sub-array":[213],"negligible":[215],"delay":[216],"overhead.":[217],"We":[218],"are":[224],"alleviated":[225],"using":[227],"circuit.":[230]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}