{"id":"https://openalex.org/W2990374524","doi":"https://doi.org/10.1109/norchip.2019.8906914","title":"MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements","display_name":"MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W2990374524","doi":"https://doi.org/10.1109/norchip.2019.8906914","mag":"2990374524"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2019.8906914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2019.8906914","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066494337","display_name":"Philipp Jungklass","orcid":null},"institutions":[{"id":"https://openalex.org/I137230718","display_name":"Ingenieurgesellschaft Auto und Verkehr (Germany)","ror":"https://ror.org/00j4h9q86","country_code":"DE","type":"company","lineage":["https://openalex.org/I137230718"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Philipp Jungklass","raw_affiliation_strings":["Ingenieurgesellschaft Auto und Verkehr GmbH Gifhorn,Germany","Ingenieurgesellschaft Auto und Verkehr GmbH Gifhorn, Germany"],"affiliations":[{"raw_affiliation_string":"Ingenieurgesellschaft Auto und Verkehr GmbH Gifhorn,Germany","institution_ids":["https://openalex.org/I137230718"]},{"raw_affiliation_string":"Ingenieurgesellschaft Auto und Verkehr GmbH Gifhorn, Germany","institution_ids":["https://openalex.org/I137230718"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039777488","display_name":"Mladen Berekovi\u0107","orcid":"https://orcid.org/0000-0003-1911-756X"},"institutions":[{"id":"https://openalex.org/I4210104073","display_name":"Becker Technologies (Germany)","ror":"https://ror.org/01hv3m305","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210104073"]},{"id":"https://openalex.org/I9341345","display_name":"University of L\u00fcbeck","ror":"https://ror.org/00t3r8h32","country_code":"DE","type":"education","lineage":["https://openalex.org/I9341345"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mladen Berekovic","raw_affiliation_strings":["University of L&#x00FC;beck, Institute of Computer Engineering,L&#x00FC;beck,Germany","University of L\u00fcbeck, Institute of Computer Engineering, L\u00fcbeck, Germany"],"affiliations":[{"raw_affiliation_string":"University of L&#x00FC;beck, Institute of Computer Engineering,L&#x00FC;beck,Germany","institution_ids":["https://openalex.org/I4210104073"]},{"raw_affiliation_string":"University of L\u00fcbeck, Institute of Computer Engineering, L\u00fcbeck, Germany","institution_ids":["https://openalex.org/I9341345"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5066494337"],"corresponding_institution_ids":["https://openalex.org/I137230718"],"apc_list":null,"apc_paid":null,"fwci":0.4815,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6297939,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8232462406158447},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.704278290271759},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6586317420005798},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6538479328155518},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.587671160697937},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5040470957756042},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4796919524669647},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.4627205729484558},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.41886287927627563},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.26918938755989075},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25317394733428955},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2381647825241089},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1907549500465393},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14816606044769287}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8232462406158447},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.704278290271759},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6586317420005798},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6538479328155518},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.587671160697937},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5040470957756042},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4796919524669647},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.4627205729484558},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.41886287927627563},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.26918938755989075},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25317394733428955},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2381647825241089},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1907549500465393},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14816606044769287},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2019.8906914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2019.8906914","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W159494641","https://openalex.org/W1989261992","https://openalex.org/W1997557955","https://openalex.org/W2061663604","https://openalex.org/W2105270383","https://openalex.org/W2118378639","https://openalex.org/W2163270257","https://openalex.org/W2169239645","https://openalex.org/W2344607722","https://openalex.org/W2487921976","https://openalex.org/W2547450728","https://openalex.org/W2888498259","https://openalex.org/W4253375448","https://openalex.org/W6675499332"],"related_works":["https://openalex.org/W2363677236","https://openalex.org/W2007964072","https://openalex.org/W2001031944","https://openalex.org/W2102140193","https://openalex.org/W2085237598","https://openalex.org/W2006835125","https://openalex.org/W1971123707","https://openalex.org/W2159870643","https://openalex.org/W2182859437","https://openalex.org/W2133121403"],"abstract_inverted_index":{"Modern":[0],"multicore":[1],"microcontrollers":[2],"for":[3,59],"systems":[4],"with":[5],"hard":[6],"real-time":[7],"requirements":[8],"increasingly":[9],"use":[10],"a":[11,82,92],"complex":[12],"memory":[13,55,75],"hierarchy":[14],"to":[15,23,52],"improve":[16],"available":[17,54],"performance":[18],"and":[19,95],"distribute":[20],"competing":[21],"accesses":[22],"separate":[24],"memories.":[25],"With":[26],"the":[27,32,35,49,53,60,79,85,89,98],"additional":[28],"computing":[29],"power":[30],"available,":[31],"complexity":[33],"of":[34,48,84],"implemented":[36],"software":[37,51],"has":[38],"also":[39],"increased.":[40],"These":[41],"two":[42],"factors":[43],"make":[44],"an":[45,56,69,73],"optimized":[46,74],"distribution":[47,76],"existing":[50],"increasing":[57],"problem":[58],"integration":[61],"into":[62],"such":[63],"systems.":[64],"Therefore,":[65],"this":[66],"article":[67],"presents":[68],"algorithm":[70],"that":[71],"calculates":[72],"based":[77],"on":[78,88],"microcontroller":[80],"used,":[81],"recording":[83],"code":[86],"execution":[87],"target":[90],"hardware,":[91],"system":[93],"description":[94],"automatically":[96],"generates":[97],"corresponding":[99],"linker":[100],"script.":[101]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
