{"id":"https://openalex.org/W2905120479","doi":"https://doi.org/10.1109/norchip.2018.8573457","title":"Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture","display_name":"Design and Implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2905120479","doi":"https://doi.org/10.1109/norchip.2018.8573457","mag":"2905120479"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2018.8573457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2018.8573457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072516473","display_name":"Sajjad Nouri","orcid":"https://orcid.org/0000-0002-5925-3681"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Sajjad Nouri","raw_affiliation_strings":["Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038279606","display_name":"Ramin G. Youvalari","orcid":"https://orcid.org/0000-0001-7260-0599"},"institutions":[{"id":"https://openalex.org/I2738502077","display_name":"Nokia (Finland)","ror":"https://ror.org/04pkc8m17","country_code":"FI","type":"company","lineage":["https://openalex.org/I2738502077"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Ramin Ghaznavi-Youvalari","raw_affiliation_strings":["Nokia Technologies, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nokia Technologies, Finland","institution_ids":["https://openalex.org/I2738502077"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jari Nurmi","raw_affiliation_strings":["Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory of Electronics and Communications Engineering, Tampere University of Technology, Finland","institution_ids":["https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3325,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59284364,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"com 25","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.714054524898529},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.7054144144058228},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.6115708947181702},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5260391235351562},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46026140451431274},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45315998792648315},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43408992886543274},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.375776469707489},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3460698127746582}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.714054524898529},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.7054144144058228},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.6115708947181702},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5260391235351562},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46026140451431274},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45315998792648315},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43408992886543274},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.375776469707489},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3460698127746582},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2018.8573457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2018.8573457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2084086197","https://openalex.org/W2089203444","https://openalex.org/W2091095932","https://openalex.org/W2105815873","https://openalex.org/W2614808262","https://openalex.org/W2678776669","https://openalex.org/W2758753160","https://openalex.org/W2768889427","https://openalex.org/W2772726042","https://openalex.org/W3184755664","https://openalex.org/W6673464759","https://openalex.org/W6676245148"],"related_works":["https://openalex.org/W1916685473","https://openalex.org/W2055682261","https://openalex.org/W1993363272","https://openalex.org/W2186390138","https://openalex.org/W2060035984","https://openalex.org/W3023876411","https://openalex.org/W123152114","https://openalex.org/W2154351074","https://openalex.org/W2362169398","https://openalex.org/W2139353707"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,92,98,102,106,114,213],"implementation":[4],"of":[5,8,55,94,101,113,116,198],"various":[6],"sizes":[7],"Discrete":[9,14],"Cosine":[10],"transform":[11],"(DCT)":[12],"and":[13,58,74,105,119,130,139,150,162,169,177,205],"Sine":[15],"Transform":[16],"(DST)":[17],"dedicated":[18],"for":[19,145,212],"High":[20],"Efficiency":[21],"Video":[22],"Coding":[23],"(HEVC)":[24],"standard":[25],"by":[26,66],"using":[27],"template-based":[28,68],"Coarse-Grained":[29],"Reconfigurable":[30],"Arrays":[31],"(CGRAs)":[32],"as":[33,208],"accelerators":[34,46,62],"on":[35,78,166,216,236],"Heterogeneous":[36],"Accelerator-Rich":[37],"Platform":[38],"(HARP).":[39],"The":[40,61,157,222],"proposal":[41],"makes":[42],"multipurpose":[43],"DCT/DST":[44],"specific":[45],"in":[47,111,137],"such":[48],"a":[49,79,84,196],"way":[50],"that":[51,127],"final":[52],"architecture":[53,224],"consists":[54],"4/8/16/32-point":[56],"DCT":[57,129],"4-point":[59,128,131],"DST.":[60],"are":[63,109,154,172],"primarily":[64],"designed":[65],"crafting":[67],"CGRA":[69],"devices":[70],"at":[71,188,233],"different":[72],"dimensions":[73],"then":[75],"arranging":[76],"them":[77],"Network-on-Chip":[80],"platform":[81,104],"along":[82],"with":[83,182],"few":[85],"RISC":[86],"cores.":[87],"In":[88],"this":[89],"research":[90],"work,":[91],"performance":[93,100,122,197],"each":[95],"DCT/DST-specific":[96],"accelerator,":[97],"collective":[99],"whole":[103],"NoC":[107],"traffic":[108],"recorded":[110],"terms":[112],"number":[115],"clock":[117,141,152],"cycles":[118,153],"several":[120],"high-level":[121],"metrics.":[123],"Conducted":[124],"experiments":[125],"show":[126],"DST":[132],"can":[133],"be":[134],"implemented":[135],"completely":[136],"54":[138],"56":[140],"cycles,":[142],"respectively,":[143],"while":[144],"8/16/32-point":[146],"DCT,":[147],"67,":[148],"179":[149],"354":[151],"required,":[155],"respectively.":[156],"achieved":[158],"total":[159],"power":[160],"dissipation":[161],"energy":[163],"consumption":[164],"based":[165],"post":[167],"placement":[168],"routing":[170],"information":[171],"equal":[173],"to":[174,195,227],"4.1":[175],"W":[176],"$10.87~\\mu":[178],"{\\mathrm":[179],"{J}}$,":[180],"respectively":[181],"256":[183],"instantiated":[184],"Processing":[185],"Elements":[186],"(PEs)":[187],"200.0":[189],"MHz":[190],"operating":[191],"frequency.":[192],"It":[193],"resulted":[194],"51.2":[199],"Giga":[200],"Operations":[201],"Per":[202],"Second":[203],"(GOPS)":[204],"12":[206],"MOPS/mW":[207],"an":[209],"architectural":[210],"constant":[211],"HARP":[214],"template":[215],"28":[217],"nm":[218],"Altera":[219],"Stratix-V":[220],"chip.":[221],"proposed":[223],"is":[225],"able":[226],"sustain":[228],"Full":[229],"HD":[230],"1080p":[231],"format":[232],"30":[234],"fps":[235],"FPGA.":[237]},"counts_by_year":[{"year":2020,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}