{"id":"https://openalex.org/W2563538317","doi":"https://doi.org/10.1109/norchip.2016.7792907","title":"Using OpenCL to rapidly prototype FPGA designs","display_name":"Using OpenCL to rapidly prototype FPGA designs","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2563538317","doi":"https://doi.org/10.1109/norchip.2016.7792907","mag":"2563538317"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2016.7792907","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2016.7792907","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Nordic Circuits and Systems Conference (NORCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002889063","display_name":"Kui Wang","orcid":"https://orcid.org/0000-0002-9654-295X"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Kui Wang","raw_affiliation_strings":["Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I166825849","display_name":"Tampere University","ror":"https://ror.org/033003e23","country_code":"FI","type":"education","lineage":["https://openalex.org/I166825849"]},{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jari Nurmi","raw_affiliation_strings":["Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communications Engineering, Tampere University of Technology, Tampere, Finland","institution_ids":["https://openalex.org/I166825849","https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"pp","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12784","display_name":"Modular Robots and Swarm Intelligence","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2210","display_name":"Mechanical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8647071719169617},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8415833115577698},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.7178540229797363},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5384711027145386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5066481232643127},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.501716136932373},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.48983094096183777},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.46908631920814514},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4290861487388611},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.41294392943382263},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4020075798034668},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3784377872943878},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3683511018753052},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13114529848098755},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12678071856498718}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8647071719169617},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8415833115577698},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.7178540229797363},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5384711027145386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5066481232643127},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.501716136932373},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.48983094096183777},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.46908631920814514},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4290861487388611},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.41294392943382263},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4020075798034668},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3784377872943878},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3683511018753052},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13114529848098755},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12678071856498718},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2016.7792907","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2016.7792907","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Nordic Circuits and Systems Conference (NORCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1518139028","https://openalex.org/W1578462120","https://openalex.org/W2065353091","https://openalex.org/W2130336316","https://openalex.org/W2147193503","https://openalex.org/W2163687928","https://openalex.org/W2188927100","https://openalex.org/W4233937284","https://openalex.org/W4234381228","https://openalex.org/W4242125880","https://openalex.org/W6684353306"],"related_works":["https://openalex.org/W2159103767","https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W3103981520","https://openalex.org/W200972441","https://openalex.org/W2038220260","https://openalex.org/W1857140530","https://openalex.org/W1545578515","https://openalex.org/W1612076744","https://openalex.org/W2152074211"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGAs)":[4],"have":[5],"gained":[6],"popularity":[7],"because":[8],"their":[9],"reconfigurability":[10],"can":[11],"speed":[12,196],"up":[13],"development":[14],"and":[15,42,47,55,82,94,107,134,155,167,192,199],"verification":[16],"with":[17],"relatively":[18],"low":[19],"cost.":[20],"However":[21],"the":[22,104,112,140,146,152,170,190,194],"deep":[23],"level":[24],"of":[25,91,126,172,185,189],"understanding":[26],"required":[27,161],"on":[28,103,111],"hardware":[29,57,78],"logic":[30,79,153],"programming":[31,48,53],"has":[32],"discouraged":[33],"many":[34],"software":[35,52],"engineers.":[36],"An":[37],"interface":[38],"between":[39],"host":[40,101],"devices":[41],"FPGAs":[43,49],"to":[44,72,114,138,178],"enable":[45],"designing":[46],"using":[50],"a":[51,86,116,163,182],"standard":[54],"encapsulating":[56],"details":[58],"is":[59],"much":[60],"desired.":[61],"In":[62],"this":[63],"paper":[64],"we":[65,97,149],"evaluate":[66],"leveraging":[67],"Open":[68],"Computing":[69],"Language":[70],"(OpenCL)":[71],"rapidly":[73],"design":[74,124],"FPGAs,":[75],"considering":[76],"both":[77],"utilization":[80,154],"efficiency":[81],"computing":[83,195],"performance.":[84,143],"On":[85],"heterogeneous":[87],"computer":[88],"system":[89],"consisting":[90],"ARM":[92,105],"processors":[93,106],"Altera":[95],"FPGA,":[96,113,191],"execute":[98],"an":[99,108],"OpenCL":[100,109,128],"program":[102],"kernel":[110],"compute":[115,136,165,174],"parametrizable":[117],"two-dimensional":[118],"Mandelbrot":[119],"fractal.":[120],"We":[121],"explore":[122],"three":[123],"aspects":[125],"adjusting":[127],"work-group":[129],"size,":[130],"coalescing":[131],"memory":[132,200],"access,":[133],"replicating":[135],"units":[137,175],"improve":[139],"FPGA":[141],"computation":[142,187],"After":[144],"optimizing":[145],"core":[147],"algorithm,":[148],"efficiently":[150],"reduced":[151],"Digital":[156],"Signal":[157],"Processing":[158],"(DSP)":[159],"blocks":[160],"for":[162],"single":[164],"unit,":[166],"successfully":[168],"increased":[169],"number":[171],"replicated":[173],"from":[176],"four":[177],"six,":[179],"thus":[180],"delivering":[181],"1.5X":[183,198],"increase":[184],"parallel":[186],"capacity":[188],"improving":[193],"by":[197,202],"bandwidth":[201],"1.7X.":[203]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}