{"id":"https://openalex.org/W2565835957","doi":"https://doi.org/10.1109/norchip.2016.7792897","title":"Hierarchical design of a low power standing wave oscillator based clock distribution network","display_name":"Hierarchical design of a low power standing wave oscillator based clock distribution network","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2565835957","doi":"https://doi.org/10.1109/norchip.2016.7792897","mag":"2565835957"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2016.7792897","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2016.7792897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Nordic Circuits and Systems Conference (NORCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100618890","display_name":"Wei Zhang","orcid":"https://orcid.org/0000-0001-7607-9235"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043781138","display_name":"Youde Hu","orcid":"https://orcid.org/0009-0003-1213-7522"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Youde Hu","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006594466","display_name":"Yuxiang Huan","orcid":"https://orcid.org/0000-0002-9155-1451"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuxiang Huan","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043039025","display_name":"Zhuo Zou","orcid":"https://orcid.org/0000-0002-8546-1329"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhuo Zou","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082571582","display_name":"Keji Cui","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Keji Cui","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005330884","display_name":"Dongxuan Bao","orcid":null},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dongxuan Bao","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067678916","display_name":"Pan Dashan","orcid":"https://orcid.org/0000-0003-3619-6802"},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dashan Pan","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002823826","display_name":"Lebo Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lebo Wang","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101565820","display_name":"Li\u2010Rong Zheng","orcid":"https://orcid.org/0000-0001-9588-0239"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lirong Zheng","raw_affiliation_strings":["State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASICs &amp; Systems, School of Information Science and Technology, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5100618890"],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4391767673"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14723304,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7316840291023254},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6936484575271606},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6668004989624023},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6470155715942383},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6397056579589844},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.6071054935455322},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5666560530662537},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5424668192863464},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5079360604286194},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5055627822875977},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5046454668045044},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41521814465522766},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3864997625350952},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38613414764404297},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3774931728839874},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27281224727630615},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2579209506511688},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.20295211672782898},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1335669755935669}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7316840291023254},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6936484575271606},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6668004989624023},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6470155715942383},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6397056579589844},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.6071054935455322},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5666560530662537},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5424668192863464},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5079360604286194},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5055627822875977},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5046454668045044},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41521814465522766},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3864997625350952},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38613414764404297},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3774931728839874},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27281224727630615},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2579209506511688},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.20295211672782898},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1335669755935669}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2016.7792897","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2016.7792897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Nordic Circuits and Systems Conference (NORCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1537744878","https://openalex.org/W1540004773","https://openalex.org/W1943708963","https://openalex.org/W1984845646","https://openalex.org/W1988317026","https://openalex.org/W2015125147","https://openalex.org/W2019298840","https://openalex.org/W2041088273","https://openalex.org/W2051282520","https://openalex.org/W2106809351","https://openalex.org/W2127083609","https://openalex.org/W2137145694","https://openalex.org/W2157488385","https://openalex.org/W2162991614","https://openalex.org/W2170639273","https://openalex.org/W3151056235","https://openalex.org/W4254534263","https://openalex.org/W6632082253","https://openalex.org/W6632308595","https://openalex.org/W6670427282","https://openalex.org/W6683079438"],"related_works":["https://openalex.org/W2496244846","https://openalex.org/W2205497670","https://openalex.org/W2085377878","https://openalex.org/W2165139624","https://openalex.org/W2169618112","https://openalex.org/W2981406251","https://openalex.org/W2483335070","https://openalex.org/W2270423654","https://openalex.org/W1933111433","https://openalex.org/W2069695849"],"abstract_inverted_index":{"This":[0,88],"paper":[1],"introduces":[2],"a":[3,23,30,54,94,121],"hierarchical":[4],"clock":[5,14,19,43,67,74,116,124],"interconnection":[6],"network":[7,32],"with":[8,120],"two-level":[9],"bufferless":[10],"standing":[11,38,62],"wave":[12,39,63],"resonant":[13],"distribution":[15],"to":[16,41,60,65,84],"minimize":[17],"the":[18,46,61,70,78],"power":[20,117],"consumption":[21,118],"in":[22,45,69],"synchronous":[24],"system.":[25],"The":[26,50],"first":[27],"level":[28,52],"is":[29,53,81,91],"serpentine":[31],"which":[33],"consists":[34],"of":[35,56],"many":[36],"coupled":[37],"oscillators":[40,64],"distribute":[42],"signals":[44,68],"whole":[47],"chip":[48],"area.":[49],"second":[51],"group":[55],"fishbone":[57,79,89],"architectures":[58],"connected":[59],"route":[66],"local":[71],"areas.":[72],"A":[73],"synthesis":[75],"flow":[76],"for":[77],"architecture":[80,90,110],"also":[82],"introduced":[83],"enable":[85],"design":[86],"automation.":[87],"studied":[92],"through":[93],"pipelined":[95],"floating-point":[96],"fused":[97],"multiply-add":[98],"module":[99],"under":[100],"28nm":[101],"standard":[102],"CMOS":[103],"process.":[104],"Simulation":[105],"results":[106],"show":[107],"that,":[108],"this":[109],"can":[111],"reduce":[112],"more":[113],"than":[114],"30%":[115],"compared":[119],"traditional":[122],"buffered":[123],"network.":[125]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
