{"id":"https://openalex.org/W2565951592","doi":"https://doi.org/10.1109/norchip.2016.7792894","title":"FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor","display_name":"FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2565951592","doi":"https://doi.org/10.1109/norchip.2016.7792894","mag":"2565951592"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2016.7792894","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2016.7792894","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Nordic Circuits and Systems Conference (NORCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000143370","display_name":"Farid Shamani","orcid":"https://orcid.org/0000-0003-4080-7469"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Farid Shamani","raw_affiliation_strings":["Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090941502","display_name":"Vida Fakour Sevom","orcid":"https://orcid.org/0000-0002-7233-3387"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Vida Fakour Sevom","raw_affiliation_strings":["Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081481126","display_name":"Tapani Ahonen","orcid":"https://orcid.org/0000-0003-0304-8790"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Tapani Ahonen","raw_affiliation_strings":["Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035297149","display_name":"Jari Nurmi","orcid":"https://orcid.org/0000-0003-2169-4606"},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jari Nurmi","raw_affiliation_strings":["Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communications Engineering, Tampere University of Technology, P.O. Box 553, FIN-33101, Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210133110"],"apc_list":null,"apc_paid":null,"fwci":0.3204,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61327023,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"8","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7643497586250305},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6830824613571167},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6445815563201904},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6266513466835022},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4738842844963074},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.46954020857810974},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.4621037244796753},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4201311469078064},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.28783780336380005},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.23990383744239807}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7643497586250305},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6830824613571167},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6445815563201904},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6266513466835022},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4738842844963074},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.46954020857810974},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.4621037244796753},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4201311469078064},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.28783780336380005},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.23990383744239807}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2016.7792894","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2016.7792894","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Nordic Circuits and Systems Conference (NORCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W7324480","https://openalex.org/W1492994364","https://openalex.org/W1558912087","https://openalex.org/W1977850862","https://openalex.org/W1981505257","https://openalex.org/W2014608904","https://openalex.org/W2184192283","https://openalex.org/W2201736731","https://openalex.org/W2214124704","https://openalex.org/W2538968901","https://openalex.org/W2542473914","https://openalex.org/W4244757065","https://openalex.org/W6633508215","https://openalex.org/W6686065017"],"related_works":["https://openalex.org/W2036206036","https://openalex.org/W4387540511","https://openalex.org/W182515070","https://openalex.org/W2993622674","https://openalex.org/W2104586137","https://openalex.org/W4309639889","https://openalex.org/W4367172762","https://openalex.org/W2026197855","https://openalex.org/W4388344772","https://openalex.org/W4280644180"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,16,38,45,49,67,73,77,83,88,92,100,107,111,130,141,157,162,173],"design,":[4],"implementation":[5],"and":[6,65,94,122],"integration":[7],"of":[8,32,48,72,76,115,153],"a":[9,21,128,146],"reconfigurable":[10],"Intellectual":[11],"Property":[12],"(IP)-based":[13],"co-processor":[14,29,50,78,95,108,132],"for":[15,178],"COFFEE":[17,84,142,163],"RISC":[18],"processor":[19,143,164],"on":[20,99],"Field":[22],"Programmable":[23],"Gate":[24],"Array":[25],"(FPGA)":[26],"device.":[27],"The":[28,150],"is":[30,51,56,79,156],"capable":[31],"communicating":[33],"with":[34,82,140,167],"peripheral":[35,169],"devices":[36,170],"through":[37],"Controller":[39],"Area":[40],"Network":[41],"(CAN)":[42],"protocol.":[43],"Although":[44],"main":[46,74,101],"target":[47],"standard":[52],"CAN":[53,69],"frames,":[54],"it":[55],"able":[57],"to":[58,63,118,161,165],"reconfigure":[59],"itself":[60],"in":[61,120,138],"run-time":[62],"receive":[64],"decode":[66],"extended":[68],"frames.":[70],"One":[71],"advantages":[75],"full":[80],"compatibility":[81],"processor's":[85],"requirements.":[86],"Furthermore,":[87],"data":[89,102],"transmission":[90],"between":[91],"core":[93,174],"introduces":[96],"no":[97],"workload":[98],"bus.":[103],"In":[104],"this":[105,154],"implementation,":[106],"could":[109],"achieve":[110],"maximum":[112],"operating":[113],"frequencies":[114],"493MHz":[116],"up":[117],"825MHz":[119],"slow":[121],"fast":[123],"timing":[124],"models,":[125],"respectively.":[126],"As":[127],"result,":[129],"implemented":[131],"gains":[133],"(at":[134],"least)":[135],"2.8x":[136],"speed-up":[137],"comparison":[139],"by":[144],"consuming":[145],"trivial":[147],"dynamic":[148],"energy.":[149],"ultimate":[151],"achievement":[152],"work":[155],"new":[158],"horizon":[159],"expanded":[160],"communicate":[166],"CAN-based":[168],"which":[171],"makes":[172],"more":[175],"versatile":[176],"even":[177],"industrial":[179],"purposes.":[180]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}