{"id":"https://openalex.org/W2215267035","doi":"https://doi.org/10.1109/norchip.2015.7364404","title":"Secured-by-design FPGA: look-up tables and switch-boxes","display_name":"Secured-by-design FPGA: look-up tables and switch-boxes","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2215267035","doi":"https://doi.org/10.1109/norchip.2015.7364404","mag":"2215267035"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2015.7364404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2015.7364404","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &amp; International Symposium on System-on-Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056223848","display_name":"Ziyad M. Almohaimeed","orcid":"https://orcid.org/0000-0002-2689-9507"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ziyad Almohaimeed","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada","institution_ids":["https://openalex.org/I212119943"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057365306","display_name":"Mihai Sima","orcid":"https://orcid.org/0000-0002-1945-5190"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mihai Sima","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada","institution_ids":["https://openalex.org/I212119943"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5056223848"],"corresponding_institution_ids":["https://openalex.org/I212119943"],"apc_list":null,"apc_paid":null,"fwci":0.8629,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.82830696,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9879000186920166,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.871610164642334},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7486494183540344},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6935499906539917},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6731621026992798},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6665279269218445},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5297637581825256},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5187482833862305},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4228478968143463},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.422324538230896},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21507033705711365},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16474390029907227},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1319923996925354},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.12263676524162292},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.12236672639846802},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08743458986282349},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.0741879940032959}],"concepts":[{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.871610164642334},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7486494183540344},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6935499906539917},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6731621026992798},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6665279269218445},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5297637581825256},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5187482833862305},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4228478968143463},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.422324538230896},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21507033705711365},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16474390029907227},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1319923996925354},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.12263676524162292},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.12236672639846802},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08743458986282349},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0741879940032959},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2015.7364404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2015.7364404","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &amp; International Symposium on System-on-Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1491520029","https://openalex.org/W1491708407","https://openalex.org/W1540392439","https://openalex.org/W1548571590","https://openalex.org/W1562542037","https://openalex.org/W1583916291","https://openalex.org/W1597200692","https://openalex.org/W1602420333","https://openalex.org/W1607006990","https://openalex.org/W1699782153","https://openalex.org/W1702900248","https://openalex.org/W1757537413","https://openalex.org/W1790072549","https://openalex.org/W1943183861","https://openalex.org/W1999470423","https://openalex.org/W2050584582","https://openalex.org/W2075544465","https://openalex.org/W2089733247","https://openalex.org/W2096361708","https://openalex.org/W2108782258","https://openalex.org/W2115402073","https://openalex.org/W2126541236","https://openalex.org/W2129356722","https://openalex.org/W2130733986","https://openalex.org/W2134398048","https://openalex.org/W2140979409","https://openalex.org/W2143307383","https://openalex.org/W2149099062","https://openalex.org/W2154909745","https://openalex.org/W2155176661","https://openalex.org/W2155383060","https://openalex.org/W6632099085","https://openalex.org/W6632864192","https://openalex.org/W6635937959","https://openalex.org/W6637406285","https://openalex.org/W6674512898","https://openalex.org/W6679414413","https://openalex.org/W6680138385","https://openalex.org/W6682554491"],"related_works":["https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W1972355764","https://openalex.org/W1993197222","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W3006681749","https://openalex.org/W2809889545","https://openalex.org/W1948588291"],"abstract_inverted_index":{"A":[0],"circuit":[1,28],"technique":[2],"based":[3,24,40],"on":[4,41],"hardware":[5],"replication":[6],"improves":[7],"the":[8,11,26,59],"robustness":[9,33,61],"of":[10],"FPGA":[12,70],"circuitry":[13],"against":[14,34,62],"dynamic":[15,64],"and/or":[16],"static":[17,66],"power":[18,67],"attacks.":[19],"Due":[20],"to":[21],"its":[22],"nMOS-MUX":[23],"structure,":[25],"proposed":[27],"also":[29],"exhibits":[30],"an":[31],"increased":[32],"early":[35],"evaluation":[36],"attacks":[37],"and":[38,46,50,65],"those":[39],"glitches.":[42],"The":[43],"secured":[44],"LUT":[45],"switch":[47],"are":[48],"3.4\u00d7":[49],"1.5\u00d7":[51],"larger":[52],"than":[53],"their":[54],"standard":[55],"counterparts,":[56],"respectively.":[57],"Given":[58],"achieved":[60],"both":[63],"attacks,":[68],"while":[69],"configurability":[71],"is":[72,75],"preserved,":[73],"this":[74],"a":[76],"good":[77],"trade-off.":[78]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
