{"id":"https://openalex.org/W2217600082","doi":"https://doi.org/10.1109/norchip.2015.7364386","title":"A fully synthesized all-digital VCO-based analog-to-digital converter","display_name":"A fully synthesized all-digital VCO-based analog-to-digital converter","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2217600082","doi":"https://doi.org/10.1109/norchip.2015.7364386","mag":"2217600082"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2015.7364386","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2015.7364386","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015336201","display_name":"Vishnu Unnikrishnan","orcid":"https://orcid.org/0000-0002-1410-3890"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Vishnu Unnikrishnan","raw_affiliation_strings":["Division of Integrated Circuits and Systems, Link\u00f6ping University, Link\u00f6ping, Sweden"],"affiliations":[{"raw_affiliation_string":"Division of Integrated Circuits and Systems, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006929776","display_name":"Srinivasa Rao Pathapati","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Srinivasa Rao Pathapati","raw_affiliation_strings":["Division of Integrated Circuits and Systems, Link\u00f6ping University, Link\u00f6ping, Sweden"],"affiliations":[{"raw_affiliation_string":"Division of Integrated Circuits and Systems, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047505166","display_name":"Mark Vesterbacka","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Mark Vesterbacka","raw_affiliation_strings":["Division of Integrated Circuits and Systems, Link\u00f6ping University, Link\u00f6ping, Sweden"],"affiliations":[{"raw_affiliation_string":"Division of Integrated Circuits and Systems, Link\u00f6ping University, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5015336201"],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":null,"apc_paid":null,"fwci":0.3541,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.63204755,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.7313017249107361},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.685238778591156},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.6761289238929749},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6343506574630737},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.544812023639679},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5051062703132629},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.46247804164886475},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.45841169357299805},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.41357824206352234},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3785593807697296},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2890770435333252},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24538633227348328},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21444183588027954},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.16602113842964172},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13974788784980774},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12683650851249695}],"concepts":[{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.7313017249107361},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.685238778591156},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.6761289238929749},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6343506574630737},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.544812023639679},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5051062703132629},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.46247804164886475},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.45841169357299805},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.41357824206352234},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3785593807697296},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2890770435333252},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24538633227348328},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21444183588027954},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.16602113842964172},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13974788784980774},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12683650851249695},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2015.7364386","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2015.7364386","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1864703715","https://openalex.org/W1973824493","https://openalex.org/W1981151840","https://openalex.org/W1983740965","https://openalex.org/W1995733996","https://openalex.org/W2018736198","https://openalex.org/W2085806603","https://openalex.org/W2126886945","https://openalex.org/W2153293882","https://openalex.org/W2157194265","https://openalex.org/W4285719527","https://openalex.org/W6639292065"],"related_works":["https://openalex.org/W2914701507","https://openalex.org/W2905521207","https://openalex.org/W2168717468","https://openalex.org/W2161345192","https://openalex.org/W2783221760","https://openalex.org/W4292071990","https://openalex.org/W3216962587","https://openalex.org/W3156142317","https://openalex.org/W169064491","https://openalex.org/W4224994410"],"abstract_inverted_index":{"Synthesis":[0],"of":[1,72],"all-digital":[2],"ADCs":[3],"leads":[4],"to":[5,80],"significant":[6],"reduction":[7],"in":[8,27,63],"design":[9,12,38,49],"cost":[10],"and":[11,33,92],"time,":[13],"besides":[14],"improving":[15],"cross-technology":[16],"portability.":[17],"In":[18],"this":[19],"work,":[20],"an":[21],"ADC":[22],"which":[23],"is":[24,30,43,52,56],"fully":[25],"described":[26],"digital":[28,37],"HDL":[29],"synthesized,":[31],"placed":[32],"routed":[34],"using":[35,58,86],"standard":[36,60],"tools.":[39],"A":[40],"VCO-based":[41],"architecture":[42],"chosen":[44],"for":[45],"its":[46],"synthesizability.":[47],"The":[48,54],"flow":[50],"employed":[51],"discussed.":[53],"circuit":[55],"synthesized":[57],"the":[59,87],"cell":[61],"library":[62],"a":[64,70],"65":[65],"nm":[66],"CMOS":[67],"process,":[68],"delivering":[69],"resolution":[71],"9":[73],"ENOB":[74],"over":[75],"10":[76],"MHz":[77],"bandwidth":[78],"according":[79],"post":[81,93],"layout":[82],"parasitic":[83],"extracted":[84],"simulations":[85],"Spectre":[88],"simulator.":[89],"Post":[90],"synthesis":[91],"place-and-route":[94],"performances":[95],"are":[96],"provided.":[97]},"counts_by_year":[{"year":2022,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}