{"id":"https://openalex.org/W4308573158","doi":"https://doi.org/10.1109/norcas57515.2022.9934617","title":"DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator","display_name":"DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator","publication_year":2022,"publication_date":"2022-10-25","ids":{"openalex":"https://openalex.org/W4308573158","doi":"https://doi.org/10.1109/norcas57515.2022.9934617"},"language":"en","primary_location":{"id":"doi:10.1109/norcas57515.2022.9934617","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norcas57515.2022.9934617","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Nordic Circuits and Systems Conference (NorCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112901542","display_name":"Mohammad Riazati","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mohammad Riazati","raw_affiliation_strings":["Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063193249","display_name":"Masoud Daneshtalab","orcid":"https://orcid.org/0000-0001-6289-1521"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Masoud Daneshtalab","raw_affiliation_strings":["Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052013615","display_name":"Mikael Sj\u00f6din","orcid":"https://orcid.org/0000-0001-7586-0409"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mikael Sjodin","raw_affiliation_strings":["Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062612658","display_name":"Bj\u00f6rn Lisper","orcid":"https://orcid.org/0000-0001-5297-6548"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bjorn Lisper","raw_affiliation_strings":["Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Heterogeneous Systems Research Group, Mälardalen University,Västerås,Sweden","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2176,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.49082835,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"73","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8081642389297485},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6828234791755676},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6459347605705261},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6272199153900146},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.6254171133041382},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.5943855047225952},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.51985102891922},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.45049890875816345},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.43709856271743774},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4275299906730652},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38680917024612427},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35604751110076904},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2758222222328186},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.20101478695869446}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8081642389297485},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6828234791755676},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6459347605705261},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6272199153900146},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.6254171133041382},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.5943855047225952},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.51985102891922},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.45049890875816345},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.43709856271743774},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4275299906730652},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38680917024612427},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35604751110076904},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2758222222328186},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.20101478695869446},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norcas57515.2022.9934617","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norcas57515.2022.9934617","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Nordic Circuits and Systems Conference (NorCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.5699999928474426}],"awards":[],"funders":[{"id":"https://openalex.org/F4320338080","display_name":"European Social Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1686810756","https://openalex.org/W2112796928","https://openalex.org/W2276486856","https://openalex.org/W2591882361","https://openalex.org/W2616014673","https://openalex.org/W2727238169","https://openalex.org/W2782904295","https://openalex.org/W2798084934","https://openalex.org/W2810861508","https://openalex.org/W2896983500","https://openalex.org/W2947420904","https://openalex.org/W2950598802","https://openalex.org/W2996011401","https://openalex.org/W3000394359","https://openalex.org/W3014927913","https://openalex.org/W3016065865","https://openalex.org/W3099047006","https://openalex.org/W3101493857","https://openalex.org/W3116598958","https://openalex.org/W3174263468","https://openalex.org/W3211485653","https://openalex.org/W3216300721","https://openalex.org/W4242577057","https://openalex.org/W4294691834","https://openalex.org/W6637373629","https://openalex.org/W6748111074","https://openalex.org/W6763105624","https://openalex.org/W6775652321","https://openalex.org/W6791113163"],"related_works":["https://openalex.org/W2788804672","https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W2269990635","https://openalex.org/W3146054601","https://openalex.org/W1777852485","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W4313484792","https://openalex.org/W4282568311"],"abstract_inverted_index":{"Deep":[0],"Neural":[1],"Networks":[2],"(DNNs)":[3],"are":[4,209,212],"now":[5],"widely":[6,43],"adopted":[7],"to":[8,16,64,99,125,131,144,149,157,181,214],"solve":[9],"various":[10,189],"problems":[11],"ranging":[12],"from":[13,200],"speech":[14],"recognition":[15],"image":[17],"classification.":[18],"Since":[19],"DNNs":[20],"demand":[21],"a":[22,61,65,82,119,127,139,198],"large":[23],"amount":[24],"of":[25,73,129,188,191],"processing":[26],"power,":[27],"their":[28],"implementation":[29,63],"on":[30,169],"hardware,":[31],"i.e.,":[32],"FPGA":[33,75,207],"or":[34,211],"ASIC,":[35],"has":[36],"received":[37],"much":[38],"attention.":[39],"High-level":[40],"synthesis":[41],"is":[42,76,106,142,179],"used":[44,143,217],"since":[45],"it":[46],"significantly":[47],"boosts":[48],"productivity":[49],"and":[50,52,113,185],"flexibility":[51],"requires":[53],"minimal":[54,133,158],"hardware":[55],"knowledge.":[56],"However,":[57],"when":[58],"HLS":[59,79],"transforms":[60],"C":[62,96],"Register-Transfer":[66],"Level":[67],"one,":[68],"the":[69,74,91,136,146,174,183,192,202,219],"high":[70],"parallelism":[71],"capability":[72],"not":[77,213],"well-utilized.":[78],"tools":[80],"provide":[81],"feature":[83],"called":[84],"directives":[85,105,130,147,155],"through":[86],"which":[87,109,201],"designers":[88],"can":[89,204],"guide":[90],"tool":[92],"using":[93],"some":[94],"defined":[95],"pragma":[97],"statements":[98],"improve":[100],"performance.":[101],"Nevertheless,":[102],"finding":[103],"appropriate":[104],"another":[107],"challenge,":[108],"needs":[110],"considerable":[111],"expertise":[112],"experience.":[114],"This":[115],"paper":[116],"proposes":[117],"DeepFlexiHLS,":[118],"two-stage":[120],"design":[121],"space":[122],"exploration":[123],"flow":[124],"find":[126,145,182],"set":[128],"achieve":[132],"latency.":[134,159],"In":[135,173],"first":[137],"stage,":[138,176],"partition-based":[140],"method":[141],"corresponding":[148],"each":[150],"partition.":[151],"Aggregating":[152],"all":[153],"these":[154],"leads":[156],"Experimental":[160],"results":[161,196],"show":[162],"54%":[163],"more":[164],"speed-up":[165],"than":[166],"similar":[167],"work":[168],"VGG":[170],"neural":[171],"network.":[172],"second":[175],"an":[177],"estimator":[178],"implemented":[180],"latency":[184],"resource":[186],"utilization":[187],"combinations":[190],"found":[193],"directives.":[194],"The":[195],"form":[197],"Pareto-frontier":[199],"designer":[203],"choose":[205],"if":[206],"resources":[208],"limited":[210],"be":[215],"entirely":[216],"by":[218],"DNN":[220],"module.":[221]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}