{"id":"https://openalex.org/W3095108256","doi":"https://doi.org/10.1109/nocs50636.2020.9241708","title":"Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture","display_name":"Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture","publication_year":2020,"publication_date":"2020-09-24","ids":{"openalex":"https://openalex.org/W3095108256","doi":"https://doi.org/10.1109/nocs50636.2020.9241708","mag":"3095108256"},"language":"en","primary_location":{"id":"doi:10.1109/nocs50636.2020.9241708","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nocs50636.2020.9241708","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101652468","display_name":"Hao Luan","orcid":"https://orcid.org/0000-0001-6342-4618"},"institutions":[{"id":"https://openalex.org/I4210146936","display_name":"Huawei Technologies (United States)","ror":"https://ror.org/03jyqk712","country_code":"US","type":"company","lineage":["https://openalex.org/I2250955327","https://openalex.org/I4210146936"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hao Luan","raw_affiliation_strings":["Futurewei Technologies Inc., Plano, Texas, USA"],"affiliations":[{"raw_affiliation_string":"Futurewei Technologies Inc., Plano, Texas, USA","institution_ids":["https://openalex.org/I4210146936"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002590438","display_name":"Alan Gatherer","orcid":"https://orcid.org/0000-0002-5937-8599"},"institutions":[{"id":"https://openalex.org/I4210146936","display_name":"Huawei Technologies (United States)","ror":"https://ror.org/03jyqk712","country_code":"US","type":"company","lineage":["https://openalex.org/I2250955327","https://openalex.org/I4210146936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Gatherer","raw_affiliation_strings":["Futurewei Technologies Inc., Plano, Texas, USA"],"affiliations":[{"raw_affiliation_string":"Futurewei Technologies Inc., Plano, Texas, USA","institution_ids":["https://openalex.org/I4210146936"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101652468"],"corresponding_institution_ids":["https://openalex.org/I4210146936"],"apc_list":null,"apc_paid":null,"fwci":0.4625,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.67506462,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7888562083244324},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.6636474132537842},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6383105516433716},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5483678579330444},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5367582440376282},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5324757099151611},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5277624130249023},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5146538019180298},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.5117166042327881},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.5000901222229004},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.4850844442844391},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.47809597849845886},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.47262096405029297},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.46132272481918335},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4337736964225769},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.4210668206214905},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.41806408762931824},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4132338762283325},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.39607182145118713},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3730854392051697},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3335118889808655},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25262218713760376},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15515220165252686},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13847759366035461},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.09340611100196838}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7888562083244324},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.6636474132537842},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6383105516433716},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5483678579330444},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5367582440376282},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5324757099151611},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5277624130249023},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5146538019180298},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.5117166042327881},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.5000901222229004},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.4850844442844391},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.47809597849845886},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.47262096405029297},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.46132272481918335},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4337736964225769},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.4210668206214905},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.41806408762931824},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4132338762283325},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.39607182145118713},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3730854392051697},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3335118889808655},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25262218713760376},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15515220165252686},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13847759366035461},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.09340611100196838},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nocs50636.2020.9241708","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nocs50636.2020.9241708","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2027029396","https://openalex.org/W2097219246","https://openalex.org/W2101381471","https://openalex.org/W2105996829","https://openalex.org/W2131853665","https://openalex.org/W2132829148","https://openalex.org/W2139216877","https://openalex.org/W2540279855","https://openalex.org/W2762859909","https://openalex.org/W3139940246","https://openalex.org/W3150157207","https://openalex.org/W4255804920"],"related_works":["https://openalex.org/W3180803030","https://openalex.org/W2782503170","https://openalex.org/W4243576563","https://openalex.org/W1575240748","https://openalex.org/W2565280077","https://openalex.org/W3025845664","https://openalex.org/W2043352873","https://openalex.org/W2143690511","https://openalex.org/W2145484885","https://openalex.org/W2047684617"],"abstract_inverted_index":{"Manycore":[0],"SoC":[1,130],"architectures":[2],"based":[3],"on":[4,69,196],"on-chip":[5],"shared":[6,43],"memory":[7,25,44,80,86,109,148,226],"are":[8,95],"preferred":[9],"for":[10,91,98],"flexible":[11],"and":[12,45,115,138,144,154,176,191,225],"programmable":[13],"solutions":[14],"in":[15,82,126,234],"many":[16,23,107],"application":[17,157],"domains.":[18],"However,":[19],"the":[20,33,67,70,85,129,165,183,189,205],"development":[21],"of":[22,35,106,113,118,147,158,193],"ported":[24,108],"is":[26,87,230],"becoming":[27],"increasingly":[28],"challenging":[29],"as":[30,89],"we":[31,75],"approach":[32],"end":[34],"Moores":[36],"Law":[37],"while":[38],"systems":[39],"requirements":[40],"demand":[41],"larger":[42],"more":[46],"access":[47,60,224],"ports.":[48],"Memory":[49],"can":[50],"no":[51],"longer":[52],"be":[53],"designed":[54],"simply":[55],"to":[56,123],"minimize":[57],"single":[58],"transaction":[59],"time,":[61],"but":[62],"must":[63],"take":[64],"into":[65],"account":[66],"functionality":[68],"SoC.":[71],"In":[72],"this":[73,127,194],"paper":[74],"examine":[76],"a":[77,135,199,212,231],"common":[78,232],"large":[79,92],"usage":[81],"SoC,":[83],"where":[84],"used":[88],"storage":[90],"buffers":[93],"that":[94,125,217],"then":[96],"moved":[97],"time":[99],"scheduled":[100],"processing.":[101],"We":[102,187],"merge":[103],"two":[104],"aspects":[105],"design,":[110],"combinatorial":[111],"analysis":[112,117],"interconnect,":[114],"geometric":[116],"critical":[119],"paths,":[120],"extending":[121],"both":[122],"show":[124,164],"case":[128],"performance":[131],"benefits":[132],"significantly":[133],"from":[134,198],"hierarchical,":[136],"distributed":[137],"staged":[139],"architecture":[140,167,195,210],"with":[141,152,172,220],"lower-radix":[142],"switches":[143],"fractal":[145],"randomization":[146],"bank":[149],"addressing,":[150],"along":[151],"judicious":[153],"geometry":[155],"aware":[156],"speed":[159],"up.":[160],"The":[161,209],"results":[162],"presented":[163],"new":[166],"supports":[168],"20%":[169,173],"higher":[170],"throughput":[171],"lower":[174],"latency":[175],"30%":[177],"less":[178],"interconnection":[179],"area":[180],"at":[181],"approximately":[182],"same":[184],"power":[185],"consumption.":[186],"demonstrate":[188],"flexibility":[190],"scalability":[192],"silicon":[197],"physical":[200],"design":[201,206],"perspective":[202],"by":[203],"taking":[204],"through":[207],"layout.":[208],"enables":[211],"much":[213],"easier":[214],"implementation":[215],"flow":[216],"works":[218],"well":[219],"physically":[221],"irregular":[222],"port":[223],"dominant":[227],"layout,":[228],"which":[229],"issue":[233],"real":[235],"designs.":[236]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}