{"id":"https://openalex.org/W1968917146","doi":"https://doi.org/10.1109/nocs.2009.5071454","title":"A Modeling and exploration framework for interconnect network design in the nanometer era","display_name":"A Modeling and exploration framework for interconnect network design in the nanometer era","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W1968917146","doi":"https://doi.org/10.1109/nocs.2009.5071454","mag":"1968917146"},"language":"en","primary_location":{"id":"doi:10.1109/nocs.2009.5071454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nocs.2009.5071454","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 3rd ACM/IEEE International Symposium on Networks-on-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/1721.1/54687","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089428659","display_name":"Ajay Joshi","orcid":"https://orcid.org/0000-0002-3256-9942"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ajay Joshi","raw_affiliation_strings":["Department of EECS, Massachusetts Institute of Technology, Cambridge, MA, USA","Department of EECS, Massachusetts Institute of Technology, Cambridge, USA"],"affiliations":[{"raw_affiliation_string":"Department of EECS, Massachusetts Institute of Technology, Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Department of EECS, Massachusetts Institute of Technology, Cambridge, USA","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045316705","display_name":"Fred K. Chen","orcid":"https://orcid.org/0000-0003-2809-9930"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fred Chen","raw_affiliation_strings":["Department of EECS, Massachusetts Institute of Technology, Cambridge, MA, USA","Department of EECS, Massachusetts Institute of Technology, Cambridge, USA"],"affiliations":[{"raw_affiliation_string":"Department of EECS, Massachusetts Institute of Technology, Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Department of EECS, Massachusetts Institute of Technology, Cambridge, USA","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025438151","display_name":"Vladimir Stojanovi\u0107","orcid":"https://orcid.org/0000-0001-7233-6863"},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vladimir Stojanovic","raw_affiliation_strings":["Department of EECS, Massachusetts Institute of Technology, Cambridge, MA, USA","Department of EECS, Massachusetts Institute of Technology, Cambridge, USA"],"affiliations":[{"raw_affiliation_string":"Department of EECS, Massachusetts Institute of Technology, Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"Department of EECS, Massachusetts Institute of Technology, Cambridge, USA","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5089428659"],"corresponding_institution_ids":["https://openalex.org/I63966007"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10031923,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"91"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10074","display_name":"Carbon Nanotubes in Composites","score":0.984000027179718,"subfield":{"id":"https://openalex.org/subfields/2505","display_name":"Materials Chemistry"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.876460075378418},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6091500520706177},{"id":"https://openalex.org/keywords/complement","display_name":"Complement (music)","score":0.58585125207901},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5678039193153381},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.5078280568122864},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.47849196195602417},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.44984740018844604},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4472898244857788},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.41403326392173767},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.34740114212036133},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3405723571777344},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32451170682907104},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.31029564142227173},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28293994069099426},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.19217678904533386},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1738070547580719}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.876460075378418},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6091500520706177},{"id":"https://openalex.org/C112313634","wikidata":"https://www.wikidata.org/wiki/Q7886648","display_name":"Complement (music)","level":5,"score":0.58585125207901},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5678039193153381},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.5078280568122864},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.47849196195602417},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.44984740018844604},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4472898244857788},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.41403326392173767},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.34740114212036133},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3405723571777344},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32451170682907104},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.31029564142227173},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28293994069099426},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.19217678904533386},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1738070547580719},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C127716648","wikidata":"https://www.wikidata.org/wiki/Q104053","display_name":"Phenotype","level":3,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C188082640","wikidata":"https://www.wikidata.org/wiki/Q1780899","display_name":"Complementation","level":4,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/nocs.2009.5071454","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nocs.2009.5071454","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 3rd ACM/IEEE International Symposium on Networks-on-Chip","raw_type":"proceedings-article"},{"id":"pmh:oai:dspace.mit.edu:1721.1/54687","is_oa":true,"landing_page_url":"http://hdl.handle.net/1721.1/54687","pdf_url":null,"source":{"id":"https://openalex.org/S4306400425","display_name":"DSpace@MIT (Massachusetts Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I63966007","host_organization_name":"Massachusetts Institute of Technology","host_organization_lineage":["https://openalex.org/I63966007"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE","raw_type":"http://purl.org/eprint/type/ConferencePaper"}],"best_oa_location":{"id":"pmh:oai:dspace.mit.edu:1721.1/54687","is_oa":true,"landing_page_url":"http://hdl.handle.net/1721.1/54687","pdf_url":null,"source":{"id":"https://openalex.org/S4306400425","display_name":"DSpace@MIT (Massachusetts Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I63966007","host_organization_name":"Massachusetts Institute of Technology","host_organization_lineage":["https://openalex.org/I63966007"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE","raw_type":"http://purl.org/eprint/type/ConferencePaper"},"sustainable_development_goals":[{"score":0.6800000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2155019192","https://openalex.org/W2365264209","https://openalex.org/W2014709025","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W2509431957","https://openalex.org/W2026999166","https://openalex.org/W2070694218","https://openalex.org/W2532822217"],"abstract_inverted_index":{"As":[0],"we":[1],"approach":[2,34],"serious":[3],"scaling":[4],"roadblocks":[5],"in":[6,26,40,57],"the":[7,27,41,55,58],"next":[8],"few":[9],"process":[10],"nodes,":[11],"it":[12],"is":[13],"imperative":[14],"to":[15,35,61,71],"identify":[16],"new":[17,37],"emerging":[18],"technologies":[19,39],"that":[20],"can":[21],"complement":[22],"or":[23],"supplant":[24],"CMOS":[25],"future.":[28],"We":[29],"present":[30],"an":[31],"integrated":[32],"cyclic":[33],"explore":[36],"interconnect":[38,65,69],"nanometer":[42],"era":[43],"for":[44],"manycore":[45],"systems,":[46],"where":[47],"on-chip":[48],"interconnects":[49],"are":[50],"jointly":[51],"optimized":[52],"at":[53],"all":[54],"levels":[56],"design":[59],"hierarchy":[60],"develop":[62],"a":[63],"complete":[64],"solution":[66],"-":[67],"from":[68],"technology":[70],"network":[72],"topology.":[73]},"counts_by_year":[],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
