{"id":"https://openalex.org/W2905241559","doi":"https://doi.org/10.1109/ngcas.2018.8572265","title":"Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process","display_name":"Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process","publication_year":2018,"publication_date":"2018-11-01","ids":{"openalex":"https://openalex.org/W2905241559","doi":"https://doi.org/10.1109/ngcas.2018.8572265","mag":"2905241559"},"language":"en","primary_location":{"id":"doi:10.1109/ngcas.2018.8572265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ngcas.2018.8572265","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 New Generation of CAS (NGCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023041346","display_name":"Fredrick Angelo R. Galapon","orcid":null},"institutions":[{"id":"https://openalex.org/I151746803","display_name":"NED University of Engineering and Technology","ror":"https://ror.org/05db8zr24","country_code":"PK","type":"education","lineage":["https://openalex.org/I151746803"]}],"countries":["PK"],"is_corresponding":true,"raw_author_name":"Fredrick Angelo R. Galapon","raw_affiliation_strings":["Department of Electronics Engineering, NED University of Engineering and Technology, Karachi, Pakistan"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, NED University of Engineering and Technology, Karachi, Pakistan","institution_ids":["https://openalex.org/I151746803"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022486896","display_name":"Mark Allen D. C. Agaton","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mark Allen D.C. Agaton","raw_affiliation_strings":["NXP Semiconductors, Nijmegen, AE, The Netherlands"],"affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Nijmegen, AE, The Netherlands","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001290757","display_name":"Arcel G. Leynes","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Arcel G. Leynes","raw_affiliation_strings":["Ampleon Netherlands B.V., Nijmegen, AV, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Ampleon Netherlands B.V., Nijmegen, AV, The Netherlands","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081552077","display_name":"Lemuel Neil M. Noveno","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Lemuel Neil M. Noveno","raw_affiliation_strings":["Department of Microelectronics, Delft University of Technology, Delft, CD, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics, Delft University of Technology, Delft, CD, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011476898","display_name":"Anastacia B. Alvarez","orcid":"https://orcid.org/0000-0002-9988-367X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Anastacia B. Alvarez","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007925575","display_name":"Chris Vincent Densing","orcid":"https://orcid.org/0000-0001-6908-9398"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chris Vincent J. Densing","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112421035","display_name":"John Richard E. Hizon","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"John Richard E. Hizon","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113873418","display_name":"Marc Rosales","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Marc D. Rosales","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110601472","display_name":"Maria Theresa G. de Leon","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Maria Theresa G. de Leon","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5091686340","display_name":"Rico Jossel Maestro","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rico Jossel M. Maestro","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5023041346"],"corresponding_institution_ids":["https://openalex.org/I151746803"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1424779,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"58","issue":null,"first_page":"70","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.8659292459487915},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7709380388259888},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6896857619285583},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6355516314506531},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6222851276397705},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5965710878372192},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5502389669418335},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5013282299041748},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.47649067640304565},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.45227816700935364},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4043983519077301},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26773524284362793},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.23635253310203552},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.1368701159954071},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1356048882007599},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09244981408119202}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.8659292459487915},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7709380388259888},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6896857619285583},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6355516314506531},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6222851276397705},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5965710878372192},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5502389669418335},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5013282299041748},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.47649067640304565},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.45227816700935364},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4043983519077301},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26773524284362793},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.23635253310203552},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.1368701159954071},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1356048882007599},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09244981408119202},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ngcas.2018.8572265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ngcas.2018.8572265","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 New Generation of CAS (NGCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1969826680","https://openalex.org/W2021980694","https://openalex.org/W2079269230","https://openalex.org/W2100452539","https://openalex.org/W2103309731","https://openalex.org/W2104717519","https://openalex.org/W2104845313","https://openalex.org/W2112637771","https://openalex.org/W2509603387","https://openalex.org/W2756566646","https://openalex.org/W6675750222"],"related_works":["https://openalex.org/W2301158783","https://openalex.org/W2133120878","https://openalex.org/W2376956425","https://openalex.org/W1972664199","https://openalex.org/W2369672785","https://openalex.org/W2054445359","https://openalex.org/W4378381217","https://openalex.org/W2143576345","https://openalex.org/W2905241559","https://openalex.org/W2094813099"],"abstract_inverted_index":{"A":[0],"clock":[1,33],"generator":[2,34],"is":[3,12,27],"an":[4,22,54],"important":[5],"part":[6],"of":[7,31,44,53,75,87],"most":[8,69],"systems":[9],"as":[10],"it":[11],"used":[13],"for":[14,35],"synchronization":[15],"and":[16],"data":[17],"processing.":[18],"For":[19],"low-power":[20],"operations,":[21],"all-digital":[23],"phase-locked":[24],"loop":[25],"(ADPLL)":[26],"a":[28,32,84],"suitable":[29],"implementation":[30],"wireless":[36],"sensing":[37],"applications.":[38],"Design":[39],"decisions":[40],"in":[41],"different":[42],"levels":[43],"abstraction":[45],"were":[46],"done":[47],"to":[48],"further":[49],"reduce":[50],"the":[51,72,76],"power":[52,62,85],"implemented":[55],"ADPLL.":[56],"It":[57],"was":[58],"shown":[59],"that":[60],"its":[61],"consumption":[63,86],"can":[64],"be":[65],"minimized":[66],"by":[67],"at":[68,89],"70%.":[70],"Moreover,":[71],"output":[73],"frequency":[74],"ADPLL":[77],"ranges":[78],"from":[79],"0.286":[80],"-":[81],"18MHz":[82],"with":[83],"4.606\u03bcW":[88],"18MHz.":[90]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
