{"id":"https://openalex.org/W7084101167","doi":"https://doi.org/10.1109/newcas64648.2025.11107161","title":"A Serial Transparent AXI Bridge for Cross-Chip Integration","display_name":"A Serial Transparent AXI Bridge for Cross-Chip Integration","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W7084101167","doi":"https://doi.org/10.1109/newcas64648.2025.11107161"},"language":"en","primary_location":{"id":"doi:10.1109/newcas64648.2025.11107161","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas64648.2025.11107161","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Till Fiedler","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Till Fiedler","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jakob Marten","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jakob Marten","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Dominik Langhorst","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dominik Langhorst","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"last","author":{"id":null,"display_name":"Holger Blume","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Holger Blume","raw_affiliation_strings":["Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Leibniz University Hannover,Hanover,Germany,30167","institution_ids":["https://openalex.org/I114112103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I114112103"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.6775413,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"480","last_page":"484"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T11470","display_name":"Legume Nitrogen Fixing Symbiosis","score":0.1995999962091446,"subfield":{"id":"https://openalex.org/subfields/1110","display_name":"Plant Science"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},"topics":[{"id":"https://openalex.org/T11470","display_name":"Legume Nitrogen Fixing Symbiosis","score":0.1995999962091446,"subfield":{"id":"https://openalex.org/subfields/1110","display_name":"Plant Science"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10015","display_name":"Genomics and Phylogenetic Studies","score":0.12710000574588776,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12934","display_name":"Plant and fungal interactions","score":0.05820000171661377,"subfield":{"id":"https://openalex.org/subfields/1105","display_name":"Ecology, Evolution, Behavior and Systematics"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serialization","display_name":"Serialization","score":0.8655999898910522},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.513700008392334},{"id":"https://openalex.org/keywords/firmware","display_name":"Firmware","score":0.5077000260353088},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.4860999882221222},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4489000141620636},{"id":"https://openalex.org/keywords/serial-port","display_name":"Serial port","score":0.42489999532699585},{"id":"https://openalex.org/keywords/backward-compatibility","display_name":"Backward compatibility","score":0.421999990940094},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.4169999957084656},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.3971000015735626}],"concepts":[{"id":"https://openalex.org/C52723943","wikidata":"https://www.wikidata.org/wiki/Q1127410","display_name":"Serialization","level":2,"score":0.8655999898910522},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7251999974250793},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.616599977016449},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5565999746322632},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.513700008392334},{"id":"https://openalex.org/C67212190","wikidata":"https://www.wikidata.org/wiki/Q104851","display_name":"Firmware","level":2,"score":0.5077000260353088},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.4860999882221222},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4489000141620636},{"id":"https://openalex.org/C102349902","wikidata":"https://www.wikidata.org/wiki/Q385390","display_name":"Serial port","level":3,"score":0.42489999532699585},{"id":"https://openalex.org/C20574231","wikidata":"https://www.wikidata.org/wiki/Q844605","display_name":"Backward compatibility","level":2,"score":0.421999990940094},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.4169999957084656},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.3971000015735626},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.37959998846054077},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.3750999867916107},{"id":"https://openalex.org/C100776233","wikidata":"https://www.wikidata.org/wiki/Q2532492","display_name":"Bridge (graph theory)","level":2,"score":0.3747999966144562},{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.3504999876022339},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.34869998693466187},{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.34450000524520874},{"id":"https://openalex.org/C2778012447","wikidata":"https://www.wikidata.org/wiki/Q1034415","display_name":"Scope (computer science)","level":2,"score":0.323199987411499},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.29339998960494995},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2921999990940094},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.28369998931884766},{"id":"https://openalex.org/C33762810","wikidata":"https://www.wikidata.org/wiki/Q461671","display_name":"Data integrity","level":2,"score":0.28040000796318054},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.2752000093460083},{"id":"https://openalex.org/C60448319","wikidata":"https://www.wikidata.org/wiki/Q154021","display_name":"Block cipher mode of operation","level":2,"score":0.271699994802475},{"id":"https://openalex.org/C22174128","wikidata":"https://www.wikidata.org/wiki/Q175869","display_name":"Microcode","level":2,"score":0.2651999890804291},{"id":"https://openalex.org/C152298349","wikidata":"https://www.wikidata.org/wiki/Q726868","display_name":"Datagram","level":3,"score":0.2623000144958496},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.25940001010894775},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.25099998712539673}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas64648.2025.11107161","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas64648.2025.11107161","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1977467261","https://openalex.org/W1980073965","https://openalex.org/W4378083907","https://openalex.org/W4379116059"],"related_works":[],"abstract_inverted_index":{"The":[0,91],"current":[1],"trend":[2],"toward":[3],"distributed":[4],"microelectronic":[5],"systems":[6],"is":[7,41],"creating":[8],"new":[9],"challenges":[10],"for":[11,46,60,119],"hardware":[12],"architectures.":[13],"Functional":[14],"blocks":[15],"that":[16,157],"used":[17,44],"to":[18,26,55,74,93,106,128,134,139],"reside":[19],"on":[20],"a":[21,42,104,107,161,165],"single":[22],"chip":[23,29],"now":[24],"need":[25],"communicate":[27],"across":[28],"boundaries":[30],"with":[31,87,99],"limited":[32],"pin":[33],"availability":[34],"and":[35,53,117],"data":[36,144,152,159],"integrity":[37,145],"risks.":[38],"AMBA":[39],"AXI":[40,78,130],"widely":[43],"standard":[45],"on-chip":[47],"communication":[48,109],"between":[49,76],"such":[50],"functional":[51],"blocks,":[52],"due":[54],"its":[56],"scope":[57],"not":[58],"designed":[59],"offchip":[61],"communication.":[62],"We":[63,148],"therefore":[64],"present":[65,150],"the":[66,100,112,129],"open-source":[67,166],"Serial":[68],"Transparent":[69],"AXI-Bridge":[70],"protocol,":[71],"which":[72],"aims":[73],"bridge":[75],"two":[77],"networks":[79],"by":[80],"serializing":[81],"messages,":[82],"thereby":[83],"increasing":[84],"line":[85],"utilization":[86],"minimal":[88],"performance":[89],"impact.":[90],"reduction":[92],"one":[94],"channel":[95],"per":[96],"direction,":[97],"along":[98],"mode":[101],"change":[102],"from":[103,153],"transaction-based":[105],"stream-based":[108],"approach,":[110],"reduces":[111],"number":[113],"of":[114],"pins":[115],"required":[116],"prepares":[118],"further":[120],"more":[121],"standardized":[122],"serialization":[123],"methods.":[124],"It":[125],"remains":[126],"transparent":[127],"members,":[131],"allowing":[132],"it":[133],"be":[135],"deployed":[136],"without":[137],"modification":[138],"existing":[140],"modules,":[141],"while":[142],"providing":[143],"robustness":[146],"improvements.":[147],"also":[149],"real-world":[151],"an":[154],"FPGA":[155],"design":[156],"transfers":[158],"over":[160],"loopback":[162],"card":[163],"using":[164],"VHDL":[167],"reference":[168],"implementation.":[169]},"counts_by_year":[],"updated_date":"2025-12-28T23:10:05.387466","created_date":"2025-10-10T00:00:00"}