{"id":"https://openalex.org/W4416679317","doi":"https://doi.org/10.1109/newcas64648.2025.11107079","title":"LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit","display_name":"LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W4416679317","doi":"https://doi.org/10.1109/newcas64648.2025.11107079"},"language":"en","primary_location":{"id":"doi:10.1109/newcas64648.2025.11107079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas64648.2025.11107079","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2504.11497","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104306732","display_name":"Chang Liu","orcid":"https://orcid.org/0009-0001-8819-0229"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Chang Liu","raw_affiliation_strings":["The University of Edinburgh,School of Engineering,Edinburgh,UK"],"affiliations":[{"raw_affiliation_string":"The University of Edinburgh,School of Engineering,Edinburgh,UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115637375","display_name":"Emmanuel A. Olowe","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Emmanuel A. Olowe","raw_affiliation_strings":["The University of Edinburgh,School of Engineering,Edinburgh,UK"],"affiliations":[{"raw_affiliation_string":"The University of Edinburgh,School of Engineering,Edinburgh,UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029110112","display_name":"Danial Chitnis","orcid":"https://orcid.org/0000-0003-0916-9921"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Danial Chitnis","raw_affiliation_strings":["The University of Edinburgh,School of Engineering,Edinburgh,UK"],"affiliations":[{"raw_affiliation_string":"The University of Edinburgh,School of Engineering,Edinburgh,UK","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5104306732"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.38961682,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"90","last_page":"94"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8472999930381775,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8472999930381775,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.04309999942779541,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.012500000186264515,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7849000096321106},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5526000261306763},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5343999862670898},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.427700012922287},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.37779998779296875},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.36390000581741333},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3571999967098236},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.3382999897003174}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7849000096321106},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6080999970436096},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5526000261306763},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5343999862670898},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.427700012922287},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4081000089645386},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.37779998779296875},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.36390000581741333},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3571999967098236},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3472000062465668},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.3395000100135803},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.3382999897003174},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.30869999527931213},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.30489999055862427},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.29919999837875366},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.296099990606308},{"id":"https://openalex.org/C17511633","wikidata":"https://www.wikidata.org/wiki/Q830694","display_name":"SMT placement equipment","level":3,"score":0.2906999886035919},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.28949999809265137},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2831000089645386},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.2646999955177307},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.26350000500679016},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.26030001044273376}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/newcas64648.2025.11107079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas64648.2025.11107079","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:2504.11497","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2504.11497","pdf_url":"https://arxiv.org/pdf/2504.11497","source":{"id":"https://openalex.org/S4393918464","display_name":"ArXiv.org","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2504.11497","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2504.11497","pdf_url":"https://arxiv.org/pdf/2504.11497","source":{"id":"https://openalex.org/S4393918464","display_name":"ArXiv.org","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W608372139","https://openalex.org/W1535414921","https://openalex.org/W2108613929","https://openalex.org/W2134179788","https://openalex.org/W2588897393","https://openalex.org/W3036532492","https://openalex.org/W3134954567","https://openalex.org/W3212050490","https://openalex.org/W4213423202","https://openalex.org/W4404132854"],"related_works":[],"abstract_inverted_index":{"The":[0],"design":[1,77,100],"of":[2,51,73,139,198,216],"Analog":[3],"and":[4,36,48,78,115,119,146,153,172,185],"Mixed-Signal":[5],"(AMS)":[6],"integrated":[7],"circuits":[8,129],"(ICs)":[9],"often":[10],"involves":[11],"significant":[12,64],"manual":[13],"effort,":[14],"especially":[15],"during":[16],"the":[17,84,104,124,137,155,207,214],"transistor":[18,85],"sizing":[19,86,105],"process.":[20,87,106],"While":[21],"Machine":[22],"Learning":[23],"techniques":[24],"in":[25,33,75,103],"Electronic":[26],"Design":[27],"Automation":[28],"(EDA)":[29],"have":[30,62],"shown":[31],"promise":[32],"reducing":[34],"complexity":[35],"minimizing":[37],"human":[38],"intervention,":[39],"they":[40],"still":[41],"face":[42],"challenges":[43],"such":[44],"as":[45],"numerous":[46],"iterations":[47],"a":[49,70],"lack":[50],"knowledge":[52,74],"about":[53],"AMS":[54,98,220],"circuit":[55,76,99,112,178,221],"design.":[56,222],"Recently,":[57],"Large":[58],"Language":[59],"Models":[60],"(LLMs)":[61],"demonstrated":[63],"potential":[65,81,215],"across":[66,149],"various":[67],"fields,":[68],"showing":[69],"certain":[71],"level":[72],"indicating":[79],"their":[80,144],"to":[82,101,130,142,200,218],"automate":[83],"In":[88],"this":[89,211],"work,":[90],"we":[91,186],"propose":[92],"an":[93,165],"LLM-based":[94],"AI":[95],"agent":[96,125],"for":[97,161,205],"assist":[102],"By":[107],"integrating":[108],"LLMs":[109,141,217],"with":[110,168],"external":[111],"simulation":[113],"tools":[114],"data":[116],"analysis":[117],"functions":[118],"employing":[120],"prompt":[121],"engineering":[122],"strategies,":[123],"successfully":[126],"optimized":[127],"multiple":[128],"achieve":[131],"target":[132,208],"performance":[133,138,183,192],"metrics.":[134],"We":[135],"evaluated":[136,180],"different":[140],"assess":[143],"applicability":[145],"optimization":[147],"effectiveness":[148],"seven":[150],"basic":[151],"circuits,":[152],"selected":[154],"best-performing":[156],"model":[157],"Claude":[158],"3.5":[159],"Sonnet":[160],"further":[162],"exploration":[163],"on":[164],"operational":[166],"amplifier,":[167],"complementary":[169],"input":[170],"stage":[171],"class":[173],"AB":[174],"output":[175],"stage.":[176],"This":[177],"was":[179,203],"against":[181],"nine":[182],"metrics,":[184],"conducted":[187],"experiments":[188],"under":[189],"three":[190],"distinct":[191],"requirement":[193],"groups.":[194],"A":[195],"success":[196],"rate":[197],"up":[199],"60":[201],"%":[202],"achieved":[204],"reaching":[206],"requirements.":[209],"Overall,":[210],"work":[212],"demonstrates":[213],"improve":[219]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-10-10T00:00:00"}