{"id":"https://openalex.org/W7084111396","doi":"https://doi.org/10.1109/newcas64648.2025.11107015","title":"A Logic-Compatible 2T Gain-Cell eDRAM in 40-nm CMOS Process","display_name":"A Logic-Compatible 2T Gain-Cell eDRAM in 40-nm CMOS Process","publication_year":2025,"publication_date":"2025-06-22","ids":{"openalex":"https://openalex.org/W7084111396","doi":"https://doi.org/10.1109/newcas64648.2025.11107015"},"language":"en","primary_location":{"id":"doi:10.1109/newcas64648.2025.11107015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas64648.2025.11107015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Chia-Yu Chu","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Yu Chu","raw_affiliation_strings":["National Tsing Hua University,Department of Electrical Engineering,Hsinchu,Taiwan,30013"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University,Department of Electrical Engineering,Hsinchu,Taiwan,30013","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ping-Hsuan Hsieh","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ping-Hsuan Hsieh","raw_affiliation_strings":["National Tsing Hua University,Department of Electrical Engineering,Hsinchu,Taiwan,30013"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University,Department of Electrical Engineering,Hsinchu,Taiwan,30013","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":null,"display_name":"Chung-Yi Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Yi Wang","raw_affiliation_strings":["National Yang Ming Chiao Tung University,Department of Microelectronics,Hsinchu,Taiwan,30010"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Yang Ming Chiao Tung University,Department of Microelectronics,Hsinchu,Taiwan,30010","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":22.1912,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.99270557,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"251","last_page":"255"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T12532","display_name":"Historical and Cultural Archaeology Studies","score":0.367000013589859,"subfield":{"id":"https://openalex.org/subfields/3314","display_name":"Anthropology"},"field":{"id":"https://openalex.org/fields/33","display_name":"Social Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},"topics":[{"id":"https://openalex.org/T12532","display_name":"Historical and Cultural Archaeology Studies","score":0.367000013589859,"subfield":{"id":"https://openalex.org/subfields/3314","display_name":"Anthropology"},"field":{"id":"https://openalex.org/fields/33","display_name":"Social Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},{"id":"https://openalex.org/T10087","display_name":"Archaeology and ancient environmental studies","score":0.120899997651577,"subfield":{"id":"https://openalex.org/subfields/1911","display_name":"Paleontology"},"field":{"id":"https://openalex.org/fields/19","display_name":"Earth and Planetary Sciences"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10421","display_name":"Pleistocene-Era Hominins and Archaeology","score":0.042899999767541885,"subfield":{"id":"https://openalex.org/subfields/3314","display_name":"Anthropology"},"field":{"id":"https://openalex.org/fields/33","display_name":"Social Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.8219000101089478},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7491999864578247},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6600000262260437},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.6323000192642212},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.5321999788284302},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5085999965667725},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46209999918937683},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4316999912261963},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.37689998745918274}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8219000101089478},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7491999864578247},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6600000262260437},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.6323000192642212},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.5321999788284302},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5085999965667725},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4986000061035156},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46209999918937683},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45899999141693115},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43619999289512634},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4316999912261963},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3831999897956848},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.37689998745918274},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37400001287460327},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.36410000920295715},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3628000020980835},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.30820000171661377},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.3068999946117401},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.28679999709129333},{"id":"https://openalex.org/C3020018676","wikidata":"https://www.wikidata.org/wiki/Q170050","display_name":"Retention time","level":2,"score":0.28450000286102295},{"id":"https://openalex.org/C163985040","wikidata":"https://www.wikidata.org/wiki/Q1172399","display_name":"Data acquisition","level":2,"score":0.27950000762939453},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.27489998936653137},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.26190000772476196},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.25769999623298645},{"id":"https://openalex.org/C88182573","wikidata":"https://www.wikidata.org/wiki/Q1139740","display_name":"High voltage","level":3,"score":0.2572000026702881},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.25609999895095825},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.2524999976158142}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas64648.2025.11107015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas64648.2025.11107015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8287575244903564}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2002293402","https://openalex.org/W2070905822","https://openalex.org/W2163518473","https://openalex.org/W2211199084","https://openalex.org/W2342496780","https://openalex.org/W2733005606","https://openalex.org/W2754347129","https://openalex.org/W2800944932","https://openalex.org/W3015947796","https://openalex.org/W3039427525","https://openalex.org/W3210205727","https://openalex.org/W4285079178","https://openalex.org/W4313291353"],"related_works":[],"abstract_inverted_index":{"In":[0,42],"recent":[1],"years,":[2],"gain-cell":[3],"embedded":[4],"DRAM":[5],"(GC-eDRAM)":[6],"becomes":[7],"an":[8,90],"emerging":[9],"alternative":[10],"for":[11,22],"SRAM":[12],"due":[13],"to":[14,30,37],"its":[15],"high-density,":[16],"low-leakage":[17],"power,":[18],"and":[19,36,73,79,85,89],"fully":[20],"logic-compatible":[21],"system-on-chip":[23],"(SoC)":[24],"design.":[25],"However,":[26],"it":[27],"remains":[28],"challenging":[29],"lengthen":[31],"the":[32,39,68,77,98],"data":[33,84],"retention":[34,59],"time":[35,60],"decrease":[38],"refresh":[40,99],"power.":[41],"this":[43],"work,":[44],"we":[45],"propose":[46],"a$1-\\text{kb}$GC-eDRAM":[47],"in$40-\\text{nm}$technology":[48],"that,":[49],"with":[50],"a":[51,105],"unit-cell":[52],"area":[53],"of$0.52":[54],"\\mu":[55],"\\mathrm{m}^{2}$,":[56],"achieves$22.6-\\mu":[57],"\\mathrm{s}$data":[58],"at$\\mathbf{3":[61],"0":[62,63],"K}$.":[64],"This":[65],"design":[66],"features":[67],"combination":[69],"of":[70,109],"I/O":[71],"PMOS":[72,75],"core":[74],"as":[76],"write":[78],"read":[80],"transistors,":[81],"carefully":[82],"chosen":[83],"control":[86],"voltage":[87],"levels,":[88],"inverter-based":[91],"readout":[92],"circuit.":[93],"Measurement":[94],"results":[95],"further":[96],"demonstrate":[97],"power":[100],"of$2.96":[101],"\\text{mW}":[102],"/":[103],"\\text{Mb}$and":[104],"maximum":[106],"operating":[107],"frequency":[108],"1.14":[110],"GHz":[111],"at$1.1-\\mathrm{V}$supply.":[112]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}