{"id":"https://openalex.org/W4402571866","doi":"https://doi.org/10.1109/newcas58973.2024.10666368","title":"An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture","display_name":"An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture","publication_year":2024,"publication_date":"2024-06-16","ids":{"openalex":"https://openalex.org/W4402571866","doi":"https://doi.org/10.1109/newcas58973.2024.10666368"},"language":"en","primary_location":{"id":"doi:10.1109/newcas58973.2024.10666368","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas58973.2024.10666368","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111197293","display_name":"Anmol Singla","orcid":null},"institutions":[{"id":"https://openalex.org/I8778637","display_name":"National Institute of Technology Srinagar","ror":"https://ror.org/03sfwvw54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I8778637"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anmol Singla","raw_affiliation_strings":["Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India","institution_ids":["https://openalex.org/I8778637"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081698284","display_name":"Dinesh Kushwaha","orcid":"https://orcid.org/0000-0003-3446-5909"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dinesh Kushwaha","raw_affiliation_strings":["Electronics and Communication Enginnering, IIT Roorkee,Roorkee,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Communication Enginnering, IIT Roorkee,Roorkee,India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107287830","display_name":"Gulyawar Aman","orcid":null},"institutions":[{"id":"https://openalex.org/I8778637","display_name":"National Institute of Technology Srinagar","ror":"https://ror.org/03sfwvw54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I8778637"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Gulyawar Aman","raw_affiliation_strings":["Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India","institution_ids":["https://openalex.org/I8778637"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111328797","display_name":"Shubhradin Chakraborty","orcid":null},"institutions":[{"id":"https://openalex.org/I98210582","display_name":"Rajiv Gandhi Institute of Petroleum Technology","ror":"https://ror.org/00n7swc17","country_code":"IN","type":"education","lineage":["https://openalex.org/I98210582"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shubhradin Chakraborty","raw_affiliation_strings":["Electronics Engineering, Rajiv Gandhi Institute of Petroleum Technology,Jais,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Engineering, Rajiv Gandhi Institute of Petroleum Technology,Jais,India","institution_ids":["https://openalex.org/I98210582"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102022884","display_name":"Abhishek Goel","orcid":"https://orcid.org/0000-0002-3788-9259"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abhishek Goel","raw_affiliation_strings":["Electronics and Communication Enginnering, IIT Roorkee,Roorkee,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Communication Enginnering, IIT Roorkee,Roorkee,India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031850929","display_name":"Anand Bulusu","orcid":"https://orcid.org/0000-0002-3986-3730"},"institutions":[{"id":"https://openalex.org/I8778637","display_name":"National Institute of Technology Srinagar","ror":"https://ror.org/03sfwvw54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I8778637"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anand Bulusu","raw_affiliation_strings":["Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India","institution_ids":["https://openalex.org/I8778637"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064560509","display_name":"Sudeb Dasgupta","orcid":"https://orcid.org/0000-0002-4044-1594"},"institutions":[{"id":"https://openalex.org/I8778637","display_name":"National Institute of Technology Srinagar","ror":"https://ror.org/03sfwvw54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I8778637"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sudeb Dasgupta","raw_affiliation_strings":["Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Electronics Engineering, National Institute of Technology,Srinagar,Uttarakhand,India","institution_ids":["https://openalex.org/I8778637"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.6355,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.95791299,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"233","last_page":"237"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7101587653160095},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7091944217681885},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6440125703811646},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5114563703536987},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.46975257992744446},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45310893654823303},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.44500306248664856},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44009628891944885},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36324334144592285},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.31197500228881836},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20727956295013428},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07409876585006714}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7101587653160095},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7091944217681885},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6440125703811646},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5114563703536987},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.46975257992744446},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45310893654823303},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.44500306248664856},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44009628891944885},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36324334144592285},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.31197500228881836},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20727956295013428},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07409876585006714},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas58973.2024.10666368","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas58973.2024.10666368","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321977","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1995562189","https://openalex.org/W2591601611","https://openalex.org/W2896934366","https://openalex.org/W2899641901","https://openalex.org/W2966524683","https://openalex.org/W3026786299","https://openalex.org/W3048814057","https://openalex.org/W3170773788","https://openalex.org/W3215945854","https://openalex.org/W4200359890","https://openalex.org/W4210923376","https://openalex.org/W4226477664","https://openalex.org/W4294691870","https://openalex.org/W4295956872","https://openalex.org/W4311217680","https://openalex.org/W4312645804","https://openalex.org/W4312951380","https://openalex.org/W4312978570","https://openalex.org/W4364296667","https://openalex.org/W4383501736"],"related_works":["https://openalex.org/W2189053673","https://openalex.org/W4319596555","https://openalex.org/W3200702775","https://openalex.org/W2186356227","https://openalex.org/W2026052914","https://openalex.org/W2149373426","https://openalex.org/W2561005478","https://openalex.org/W2043352873","https://openalex.org/W4381612949","https://openalex.org/W2546565930"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,93,111,164],"energy-efficient":[4],"and":[5,15,42,140,159,166,181],"low-latency":[6],"approach":[7,29,57,153],"for":[8,169,188],"performing":[9,170],"a":[10,25,37,55,70,100,125],"large":[11],"number":[12],"of":[13,96,102,113,128],"Multiply":[14],"Accumulate":[16],"(MAC)":[17],"operations":[18,172],"in":[19,144,173],"Deep":[20],"Neural":[21],"Networks":[22],"(DNNs)":[23],"using":[24],"Compute":[26],"In-Memory":[27],"(CIM)":[28],"based":[30,53],"on":[31,54,117],"SRAM.":[32],"The":[33,80,89,121],"proposed":[34,90,151],"design":[35,91,185],"utilizes":[36],"lOTlC":[38],"bit-cell,":[39,157],"offering":[40],"robustness":[41],"linearity":[43],"advantages":[44],"over":[45],"competing":[46],"architectures.":[47],"A":[48],"Voltage-to-Time":[49],"Converter":[50,72],"(VTC)":[51],"cell":[52],"current-starve":[56],"is":[58,74],"employed":[59],"to":[60,66,76,135],"convert":[61],"the":[62,108,118,150,155],"analog":[63],"voltage":[64],"domain":[65],"time":[67],"domain.":[68],"Furthermore,":[69],"Time-to-Digital":[71],"(TDC)":[73],"utilized":[75],"reduce":[77],"hardware":[78,141],"costs.":[79],"implemented$128\\times":[81],"64$SRAM-based":[82],"CIM":[83,152],"macro":[84,109],"uses":[85],"45nm":[86],"CMOS":[87],"technology.":[88],"achieves":[92,110,124],"energy":[94,177],"efficiency":[95],"740.39":[97],"TOPS/W":[98],"with":[99,154],"latency":[101],"4":[103],"nanoseconds":[104],"at":[105],"1.0V.":[106],"Additionally,":[107],"accuracy":[112,182],"94.4%":[114],"when":[115],"evaluated":[116],"MNIST":[119],"dataset.":[120],"designed":[122],"architecture":[123],"high":[126],"throughput":[127],"4096":[129],"GOPS,":[130],"effectively":[131],"addressing":[132],"issues":[133],"related":[134],"read-write":[136],"disturb,":[137],"power":[138],"consumption,":[139],"costs":[142],"prevalent":[143],"existing":[145],"state-of-the-art":[146],"solutions.":[147],"By":[148],"integrating":[149],"10TlC":[156],"VTC,":[158],"TDC,":[160],"this":[161,184],"research":[162],"offers":[163],"efficient":[165],"cost-effective":[167],"solution":[168],"MAC":[171],"DNNs.":[174],"High":[175],"throughput,":[176],"efficiency,":[178],"low":[179],"latency,":[180],"make":[183],"highly":[186],"promising":[187],"accelerating":[189],"deep-learning":[190],"tasks.":[191]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
