{"id":"https://openalex.org/W4385624859","doi":"https://doi.org/10.1109/newcas57931.2023.10198062","title":"UPF-Aware CDC Structural Verification on RTL","display_name":"UPF-Aware CDC Structural Verification on RTL","publication_year":2023,"publication_date":"2023-06-26","ids":{"openalex":"https://openalex.org/W4385624859","doi":"https://doi.org/10.1109/newcas57931.2023.10198062"},"language":"en","primary_location":{"id":"doi:10.1109/newcas57931.2023.10198062","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/newcas57931.2023.10198062","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092835379","display_name":"Diana Kalel","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Diana Kalel","raw_affiliation_strings":["CPU division STMicroelectronics,Grenoble,France","CPU division STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CPU division STMicroelectronics,Grenoble,France","institution_ids":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"raw_affiliation_string":"CPU division STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069426138","display_name":"Jean-Christophe Brignone","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Jean-Christophe Brignone","raw_affiliation_strings":["CPU division STMicroelectronics,Grenoble,France","CPU division STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CPU division STMicroelectronics,Grenoble,France","institution_ids":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"raw_affiliation_string":"CPU division STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5092835380","display_name":"Irene Serre","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Irene Serre","raw_affiliation_strings":["CPU division STMicroelectronics,Grenoble,France","CPU division STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CPU division STMicroelectronics,Grenoble,France","institution_ids":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"raw_affiliation_string":"CPU division STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5092835381","display_name":"Julian Massicot","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Julian Massicot","raw_affiliation_strings":["CPU division STMicroelectronics,Grenoble,France","CPU division STMicroelectronics, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CPU division STMicroelectronics,Grenoble,France","institution_ids":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]},{"raw_affiliation_string":"CPU division STMicroelectronics, Grenoble, France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5092835382","display_name":"Jerome Avezou","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Jerome Avezou","raw_affiliation_strings":["Verification, Customer Success Group Synopsys,Sophia Antipolis,France","Verification, Customer Success Group Synopsys, Sophia Antipolis, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Verification, Customer Success Group Synopsys,Sophia Antipolis,France","institution_ids":["https://openalex.org/I1335490905"]},{"raw_affiliation_string":"Verification, Customer Success Group Synopsys, Sophia Antipolis, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09403606,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8178667426109314},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7689255475997925},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7265419363975525},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5058736205101013},{"id":"https://openalex.org/keywords/power-domains","display_name":"Power domains","score":0.46906256675720215},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.4684436619281769},{"id":"https://openalex.org/keywords/masking","display_name":"Masking (illustration)","score":0.4436004161834717},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.41515052318573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40471720695495605},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.37694695591926575},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.17848175764083862},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16475948691368103},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.156672865152359}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8178667426109314},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7689255475997925},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7265419363975525},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5058736205101013},{"id":"https://openalex.org/C16021271","wikidata":"https://www.wikidata.org/wiki/Q17152552","display_name":"Power domains","level":3,"score":0.46906256675720215},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.4684436619281769},{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.4436004161834717},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.41515052318573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40471720695495605},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.37694695591926575},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.17848175764083862},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16475948691368103},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.156672865152359},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas57931.2023.10198062","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/newcas57931.2023.10198062","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1903246676","https://openalex.org/W2272517077","https://openalex.org/W2907169518"],"related_works":["https://openalex.org/W2105593427","https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W2106507440","https://openalex.org/W3209085687","https://openalex.org/W2108860137","https://openalex.org/W2125238773","https://openalex.org/W2153955347","https://openalex.org/W1928822090","https://openalex.org/W75359960"],"abstract_inverted_index":{"Current":[0],"ICs":[1],"(Integrated":[2],"Circuits)":[3],"include":[4],"millions-of-gates":[5],"IPs":[6],"(Intellectual":[7],"Properties)":[8],"that":[9],"interface":[10],"to":[11,20,44,58,118,130],"each":[12],"other":[13],"through":[14],"multiple":[15],"asynchronous":[16,26],"clock":[17],"domains.":[18],"Therefore,":[19],"ensure":[21],"the":[22,25,66,89,109,124,131],"correctness":[23],"of":[24,40,80,101,111,127],"communications,":[27],"exhaustive":[28],"CDC":[29,48,90,102],"(Clock":[30],"Domain":[31],"Crossing)":[32],"structural":[33,91],"verification":[34,42],"must":[35],"be":[36,59],"performed.":[37],"The":[38,78],"target":[39],"this":[41],"is":[43,72,116],"detect":[45],"all":[46,56],"possible":[47],"paths":[49],"present":[50],"in":[51],"a":[52,76,85,98],"design.":[53],"This":[54],"requires":[55],"clocks":[57],"well":[60],"defined":[61],"and":[62,113],"concurrently":[63],"propagated.":[64],"Including":[65],"UPF":[67],"(Unified":[68],"Power":[69],"Format)":[70],"file":[71],"crucial":[73],"for":[74,88],"such":[75],"verification.":[77,92],"presence":[79],"these":[81],"low-power":[82],"components":[83],"poses":[84],"new":[86],"challenge":[87],"However,":[93],"their":[94],"absence":[95],"risks":[96],"masking":[97],"considerable":[99],"number":[100],"problems.":[103],"An":[104],"open":[105],"Tcl":[106],"tool":[107],"allowing":[108],"elaboration":[110],"additional":[112],"custom":[114],"features":[115],"used":[117],"demonstrate":[119],"how":[120],"our":[121],"approach":[122],"increased":[123],"QoR":[125],"(Quality":[126],"Results)":[128],"compared":[129],"native":[132],"platform.":[133]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}