{"id":"https://openalex.org/W3048013844","doi":"https://doi.org/10.1109/newcas49341.2020.9159766","title":"Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy","display_name":"Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy","publication_year":2020,"publication_date":"2020-06-01","ids":{"openalex":"https://openalex.org/W3048013844","doi":"https://doi.org/10.1109/newcas49341.2020.9159766","mag":"3048013844"},"language":"en","primary_location":{"id":"doi:10.1109/newcas49341.2020.9159766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas49341.2020.9159766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078655536","display_name":"Antonio Lopez-Angulo","orcid":"https://orcid.org/0000-0002-4548-3638"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Lopez-Angulo","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC \u2013 Universidad de Sevilla), Av. Am\u00e9rico Vespucio 28., Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC \u2013 Universidad de Sevilla), Av. Am\u00e9rico Vespucio 28., Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072282417","display_name":"Antonio Gin\u00e9s","orcid":"https://orcid.org/0000-0001-5272-5802"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Gines","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC \u2013 Universidad de Sevilla), Av. Am\u00e9rico Vespucio 28., Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC \u2013 Universidad de Sevilla), Av. Am\u00e9rico Vespucio 28., Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091600572","display_name":"E. Peral\u00edas","orcid":"https://orcid.org/0000-0003-0629-0785"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Eduardo Peralias","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC \u2013 Universidad de Sevilla), Av. Am\u00e9rico Vespucio 28., Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC \u2013 Universidad de Sevilla), Av. Am\u00e9rico Vespucio 28., Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3533,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78298343,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"130","last_page":"133"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7824088335037231},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.7668801546096802},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.7541289329528809},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5806096196174622},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5007450580596924},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.43083733320236206},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21613088250160217},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21024057269096375},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1409423053264618},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11820763349533081},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.08997997641563416}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7824088335037231},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.7668801546096802},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.7541289329528809},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5806096196174622},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5007450580596924},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.43083733320236206},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21613088250160217},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21024057269096375},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1409423053264618},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11820763349533081},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.08997997641563416},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas49341.2020.9159766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas49341.2020.9159766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1584667699","https://openalex.org/W2052276427","https://openalex.org/W2744967592","https://openalex.org/W2913165060","https://openalex.org/W3091332734","https://openalex.org/W6634913629"],"related_works":["https://openalex.org/W2354365353","https://openalex.org/W1988437325","https://openalex.org/W2811287415","https://openalex.org/W2354835317","https://openalex.org/W2171140818","https://openalex.org/W2130152888","https://openalex.org/W2542018682","https://openalex.org/W2003918017","https://openalex.org/W4252544904","https://openalex.org/W2906102508"],"abstract_inverted_index":{"This":[0],"work":[1],"introduces":[2],"a":[3,78],"digital":[4],"technique":[5],"to":[6,51],"measure":[7],"and":[8],"correct":[9],"the":[10,23,39,46,49,54,62,69],"mismatch":[11],"between":[12],"capacitors":[13,47],"in":[14,48,77],"SAR":[15,81],"ADCs":[16],"with":[17,35],"split":[18],"capacitor-based":[19],"DAC":[20],"(CDAC),":[21],"including":[22],"bridge":[24],"capacitor":[25],"impairments.":[26],"The":[27,66],"method":[28,70],"takes":[29],"advantage":[30],"of":[31,45,68],"redundancy":[32,58],"for":[33],"calibration":[34],"negligible":[36],"impact":[37],"on":[38],"analog":[40],"section.":[41],"It":[42],"reuses":[43],"some":[44],"array":[50],"also":[52],"compensate":[53],"comparison":[55],"offset,":[56],"preventing":[57],"interval":[59],"saturation":[60],"during":[61],"error":[63],"measurement":[64],"phase.":[65],"effectiveness":[67],"is":[71],"demonstrated":[72],"by":[73],"realistic":[74],"behavioral":[75],"simulations":[76],"12-bit":[79],"split-CDAC":[80],"ADC":[82],"case":[83],"study.":[84]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
