{"id":"https://openalex.org/W3002848853","doi":"https://doi.org/10.1109/newcas44328.2019.8961312","title":"A Semi-Serial Topology for Compact and Fast IMPLY-based Memristive Full Adders","display_name":"A Semi-Serial Topology for Compact and Fast IMPLY-based Memristive Full Adders","publication_year":2019,"publication_date":"2019-06-01","ids":{"openalex":"https://openalex.org/W3002848853","doi":"https://doi.org/10.1109/newcas44328.2019.8961312","mag":"3002848853"},"language":"en","primary_location":{"id":"doi:10.1109/newcas44328.2019.8961312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas44328.2019.8961312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050080301","display_name":"Nima TaheriNejad","orcid":"https://orcid.org/0000-0002-1295-0332"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"N. TaheriNejad","raw_affiliation_strings":["TU Wien,Vienna,Austria","TU Wien, Vienna, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TU Wien,Vienna,Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"TU Wien, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010503670","display_name":"Theophile Delaroche","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"T. Delaroche","raw_affiliation_strings":["University of British Columbia,Vancouver,Canada","University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia,Vancouver,Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075635327","display_name":"David Radakovits","orcid":null},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"D. Radakovits","raw_affiliation_strings":["TU Wien,Vienna,Austria","TU Wien, Vienna, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TU Wien,Vienna,Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"TU Wien, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049231448","display_name":"Shahriar Mirabbasi","orcid":"https://orcid.org/0000-0001-8852-1633"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S. Mirabbasi","raw_affiliation_strings":["University of British Columbia,Vancouver,Canada","University of British Columbia, Vancouver, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia,Vancouver,Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5050080301"],"corresponding_institution_ids":["https://openalex.org/I145847075"],"apc_list":null,"apc_paid":null,"fwci":1.4529,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.83089632,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9464582800865173},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.8620543479919434},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6834791302680969},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6252539753913879},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5267630815505981},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.5188523530960083},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4792628288269043},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45807337760925293},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4327225089073181},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.41095733642578125},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3553636372089386},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33557260036468506},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17824095487594604},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16969376802444458},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13671547174453735}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9464582800865173},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.8620543479919434},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6834791302680969},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6252539753913879},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5267630815505981},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.5188523530960083},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4792628288269043},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45807337760925293},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4327225089073181},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.41095733642578125},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3553636372089386},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33557260036468506},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17824095487594604},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16969376802444458},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13671547174453735}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas44328.2019.8961312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas44328.2019.8961312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6100000143051147}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1578783943","https://openalex.org/W1986623396","https://openalex.org/W2025674646","https://openalex.org/W2066280488","https://openalex.org/W2068007821","https://openalex.org/W2085205847","https://openalex.org/W2122148191","https://openalex.org/W2323986115","https://openalex.org/W2529457757","https://openalex.org/W2542473330","https://openalex.org/W2557703348","https://openalex.org/W2664249309","https://openalex.org/W2809226946","https://openalex.org/W6728236309"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W4295540194","https://openalex.org/W1993041309","https://openalex.org/W2064215635"],"abstract_inverted_index":{"Memristive":[0],"systems":[1],"are":[2,13,31,62],"among":[3],"the":[4,34,47,144],"emerging":[5],"technologies":[6],"that":[7],"hold":[8],"a":[9,69,86,123],"great":[10],"promise.":[11],"They":[12],"compact,":[14],"CMOS":[15],"compatible,":[16],"easy":[17],"to":[18,142],"fabricate":[19],"and":[20,37,100,112],"can":[21],"serve":[22],"for":[23,76,126],"storage":[24],"as":[25,27],"well":[26],"computation":[28],"purposes.":[29],"Adders":[30],"one":[32],"of":[33,41,46,51,89,137],"most":[35],"basic":[36],"critical":[38],"building":[39],"blocks":[40],"any":[42],"computing":[43],"system.":[44],"One":[45],"main":[48],"application":[49],"areas":[50],"memristors":[52,116],"is":[53,82,106,122],"in":[54,65,79],"Material":[55],"Implication":[56],"(IMPLY)":[57],"based":[58],"logic.":[59],"IMPLY-based":[60,97],"adders":[61,111],"implemented":[63],"either":[64],"serial,":[66],"which":[67,81,105],"has":[68],"compact":[70],"implementation":[71],"but":[72],"needs":[73],"many":[74],"steps":[75],"calculation,":[77],"or":[78,135],"parallel,":[80],"fast,":[83],"however,":[84],"requires":[85,113],"large":[87],"number":[88,136],"memristors.":[90],"In":[91],"this":[92],"paper":[93],"we":[94],"propose":[95],"an":[96],"adder":[98],"topology":[99,121],"its":[101],"respective":[102],"addition":[103],"algorithm":[104],"54-to-65%":[107],"faster":[108],"than":[109,117],"serial":[110],"46-to-76%":[114],"less":[115],"parallel":[118],"adders.":[119],"This":[120],"favorable":[124],"candidate":[125],"applications":[127],"where":[128],"neither":[129],"speed,":[130],"nor":[131],"cost":[132],"(i.e.,":[133],"area":[134],"memristors)":[138],"could":[139],"be":[140],"compromised":[141],"gain":[143],"required":[145],"performance.":[146]},"counts_by_year":[{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-05-06T08:25:59.206177","created_date":"2025-10-10T00:00:00"}
