{"id":"https://openalex.org/W2742409845","doi":"https://doi.org/10.1109/newcas.2017.8010157","title":"A data driven CGRA Overlay Architecture with embedded processors","display_name":"A data driven CGRA Overlay Architecture with embedded processors","publication_year":2017,"publication_date":"2017-06-01","ids":{"openalex":"https://openalex.org/W2742409845","doi":"https://doi.org/10.1109/newcas.2017.8010157","mag":"2742409845"},"language":"en","primary_location":{"id":"doi:10.1109/newcas.2017.8010157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas.2017.8010157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012630775","display_name":"Himan Khanzadi","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Himan Khanzadi","raw_affiliation_strings":["Electrical Engineering, Polytechnique Montr\u00e9al, Montr\u00e9al, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Polytechnique Montr\u00e9al, Montr\u00e9al, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["Electrical Engineering, Polytechnique Montr\u00e9al, Montr\u00e9al, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Polytechnique Montr\u00e9al, Montr\u00e9al, Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067086966","display_name":"Jean\u2010Pierre David","orcid":"https://orcid.org/0000-0002-7707-0483"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jean Pierre David","raw_affiliation_strings":["Electrical Engineering, Polytechnique Montr\u00e9al, Montr\u00e9al, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Polytechnique Montr\u00e9al, Montr\u00e9al, Canada","institution_ids":["https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5012630775"],"corresponding_institution_ids":["https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":0.6946,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.69479541,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"269","last_page":"272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microblaze","display_name":"MicroBlaze","score":0.8623592853546143},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8168436884880066},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7677823305130005},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.58314448595047},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5217186808586121},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.4904908537864685},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.47023600339889526},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4687262773513794},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42813485860824585},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4186001420021057},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3866668939590454},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36524683237075806},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1252579689025879}],"concepts":[{"id":"https://openalex.org/C2777575374","wikidata":"https://www.wikidata.org/wiki/Q1644704","display_name":"MicroBlaze","level":3,"score":0.8623592853546143},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8168436884880066},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7677823305130005},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.58314448595047},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5217186808586121},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.4904908537864685},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.47023600339889526},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4687262773513794},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42813485860824585},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4186001420021057},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3866668939590454},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36524683237075806},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1252579689025879},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/newcas.2017.8010157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas.2017.8010157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.polymtl.ca:38007","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/38007/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334841","display_name":"Fonds de recherche du Qu\u00e9bec \u2013 Nature et technologies","ror":"https://ror.org/00b9f9778"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W13759931","https://openalex.org/W37253703","https://openalex.org/W1485517334","https://openalex.org/W1494819527","https://openalex.org/W1927084546","https://openalex.org/W2000479655","https://openalex.org/W2052930524","https://openalex.org/W2091391896","https://openalex.org/W2123412205","https://openalex.org/W2144973879","https://openalex.org/W2150022482","https://openalex.org/W2150667319","https://openalex.org/W2158824786","https://openalex.org/W2211984920","https://openalex.org/W6600540968"],"related_works":["https://openalex.org/W2371772824","https://openalex.org/W2350519679","https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2147676121","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2108598117","https://openalex.org/W2376312311","https://openalex.org/W2354823813"],"abstract_inverted_index":{"Implementing":[0],"an":[1,29,117,127],"algorithm":[2],"on":[3,61,168],"FPGA":[4,30,55,80],"is":[5,104,120,136,159],"intrinsically":[6],"more":[7],"difficult":[8],"than":[9],"programming":[10],"a":[11,14,20,33,36,41,72,78,85,92,99,124,131,147,155,163,169],"processor":[12,125],"or":[13],"GPU.":[15],"Processor-based":[16],"implementations":[17],"\u201conly\u201d":[18],"require":[19],"program":[21],"to":[22,53,74,87,106,130,138,146,162],"control":[23],"their":[24],"pre-synthesized":[25],"data":[26,38],"path,":[27],"while":[28],"requires":[31],"that":[32,70,144],"designer":[34,73],"creates":[35],"new":[37,42],"path":[39],"and":[40,66,82,114,152],"controller":[43],"for":[44],"each":[45],"application.":[46],"Several":[47],"approaches":[48],"have":[49],"been":[50],"proposed":[51,97,112],"recently":[52],"ease":[54],"design.":[56],"The":[57],"present":[58],"work":[59],"builds":[60],"Coarse-Grained":[62],"Reconfigurable":[63],"Architectures":[64,68],"(CGRAs),":[65],"Overlay":[67],"(OAs),":[69],"allow":[71],"take":[75],"advantage":[76],"of":[77,157],"pre-compiled":[79],"architecture":[81,113],"still":[83],"provide":[84],"way":[86],"configure":[88],"the":[89,96,111,150,153],"system":[90],"at":[91],"higher":[93],"level.":[94],"In":[95],"architecture,":[98],"generic":[100],"data-driven":[101],"compute":[102],"fabric":[103],"interfaced":[105],"standard":[107],"processors.":[108],"To":[109],"validate":[110],"design":[115],"method,":[116],"illustrative":[118],"example":[119],"developed":[121],"in":[122],"which":[123],"sends":[126],"RGB":[128],"image":[129],"processing":[132],"fabric,":[133,154],"where":[134],"it":[135],"converted":[137],"Y,":[139],"Cr,":[140],"Cb.":[141],"Results":[142],"show":[143],"thanks":[145],"DMA":[148],"between":[149],"memory":[151],"speedup":[156],"50":[158],"reached":[160],"compared":[161],"pure":[164],"software":[165],"implementation":[166],"running":[167],"Microblaze":[170],"processor.":[171]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
