{"id":"https://openalex.org/W2149842526","doi":"https://doi.org/10.1109/newcas.2014.6934005","title":"An IP interface design compiler with SystemC based input specifications","display_name":"An IP interface design compiler with SystemC based input specifications","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W2149842526","doi":"https://doi.org/10.1109/newcas.2014.6934005","mag":"2149842526"},"language":"en","primary_location":{"id":"doi:10.1109/newcas.2014.6934005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas.2014.6934005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019252212","display_name":"Yin\u2010Tsung Hwang","orcid":"https://orcid.org/0000-0001-9233-0477"},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yin-Tsung Hwang","raw_affiliation_strings":["EE Department, National Chung Hsing University, Taichung, Taiwan"],"affiliations":[{"raw_affiliation_string":"EE Department, National Chung Hsing University, Taichung, Taiwan","institution_ids":["https://openalex.org/I162838928"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021263459","display_name":"Jiun-Yan Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jiun-Yan Chen","raw_affiliation_strings":["EE Department, National Chung Hsing University, Taichung, Taiwan"],"affiliations":[{"raw_affiliation_string":"EE Department, National Chung Hsing University, Taichung, Taiwan","institution_ids":["https://openalex.org/I162838928"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5019252212"],"corresponding_institution_ids":["https://openalex.org/I162838928"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16294128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"42","issue":null,"first_page":"149","last_page":"152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8759264349937439},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8666896224021912},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7033125162124634},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5807948708534241},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5502849817276001},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5350502729415894},{"id":"https://openalex.org/keywords/interface-description-language","display_name":"Interface description language","score":0.5166285634040833},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.47739285230636597},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3790110945701599},{"id":"https://openalex.org/keywords/user-interface","display_name":"User interface","score":0.27173325419425964},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19147560000419617}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8759264349937439},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8666896224021912},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7033125162124634},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5807948708534241},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5502849817276001},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5350502729415894},{"id":"https://openalex.org/C177216440","wikidata":"https://www.wikidata.org/wiki/Q1044749","display_name":"Interface description language","level":3,"score":0.5166285634040833},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.47739285230636597},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3790110945701599},{"id":"https://openalex.org/C89505385","wikidata":"https://www.wikidata.org/wiki/Q47146","display_name":"User interface","level":2,"score":0.27173325419425964},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19147560000419617},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas.2014.6934005","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas.2014.6934005","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1560082788","https://openalex.org/W2027657928","https://openalex.org/W2031991320","https://openalex.org/W2091528902","https://openalex.org/W2105199621","https://openalex.org/W2109821573","https://openalex.org/W2121099050","https://openalex.org/W2157464436","https://openalex.org/W2548983515","https://openalex.org/W4232727899","https://openalex.org/W4233440324","https://openalex.org/W6673590861"],"related_works":["https://openalex.org/W2752828786","https://openalex.org/W2242433395","https://openalex.org/W2544073398","https://openalex.org/W2548514518","https://openalex.org/W2579932084","https://openalex.org/W3206586607","https://openalex.org/W2802530065","https://openalex.org/W1831349210","https://openalex.org/W1550409889","https://openalex.org/W1603163876"],"abstract_inverted_index":{"We":[0],"present":[1],"an":[2],"interface":[3,11,45,70,82,100],"synthesis":[4,46,84,115],"tool":[5],"(design":[6],"compiler)":[7],"which":[8],"can":[9],"generate":[10],"circuits":[12],"automatically":[13],"to":[14,69],"expedite":[15],"the":[16,65,86,96,106,110,113],"IP":[17],"(silicon":[18],"intellectual":[19],"property)":[20],"integration":[21],"process":[22],"in":[23,37],"SoC":[24],"designs.":[25],"The":[26,42],"protocol":[27,74,89],"specification":[28],"issue":[29],"is":[30,40,47],"first":[31],"addressed":[32],"and":[33,59,91,105],"a":[34],"programming":[35],"paradigm":[36],"SystemC":[38],"language":[39],"developed.":[41],"methodology":[43],"for":[44,78,85,95],"next":[48],"elaborated.":[49],"Conventional":[50],"compiler":[51],"techniques":[52],"such":[53],"as":[54],"lexical":[55],"analysis,":[56],"syntax":[57],"parsing":[58],"code":[60],"generation":[61],"are":[62,103],"applied":[63],"plus":[64],"new":[66],"processing":[67],"specific":[68],"synthesis.":[71],"This":[72],"includes":[73],"signal":[75],"mapping":[76,94],"proxy":[77],"additional":[79],"semantic":[80],"information,":[81],"FSM":[83],"controller":[87],"of":[88,112],"conversion":[90],"architecture":[92],"template":[93],"underlined":[97],"hardware.":[98],"Various":[99],"design":[101],"examples":[102],"conducted":[104],"experimental":[107],"results":[108],"show":[109],"competitiveness":[111],"proposed":[114],"tool.":[116]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
