{"id":"https://openalex.org/W1984789723","doi":"https://doi.org/10.1109/newcas.2012.6329000","title":"CAD tool autogeneration of VHDL FFT for FPGA/ASIC implementation","display_name":"CAD tool autogeneration of VHDL FFT for FPGA/ASIC implementation","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W1984789723","doi":"https://doi.org/10.1109/newcas.2012.6329000","mag":"1984789723"},"language":"en","primary_location":{"id":"doi:10.1109/newcas.2012.6329000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas.2012.6329000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE International NEWCAS Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020618891","display_name":"Todd E. Schmuland","orcid":null},"institutions":[{"id":"https://openalex.org/I90871651","display_name":"University of Toledo","ror":"https://ror.org/01pbdzh19","country_code":"US","type":"education","lineage":["https://openalex.org/I90871651"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Todd E. Schmuland","raw_affiliation_strings":["Department of Electrical Engineering & Computer Science, The University of Toledo, Toledo, OH","Department of Electrical Engineering and Computer Science, The University of Toledo, OH 43606, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Computer Science, The University of Toledo, Toledo, OH","institution_ids":["https://openalex.org/I90871651"]},{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, The University of Toledo, OH 43606, USA","institution_ids":["https://openalex.org/I90871651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101868251","display_name":"Mohsin M. Jamali","orcid":"https://orcid.org/0000-0002-1837-6546"},"institutions":[{"id":"https://openalex.org/I90871651","display_name":"University of Toledo","ror":"https://ror.org/01pbdzh19","country_code":"US","type":"education","lineage":["https://openalex.org/I90871651"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohsin M. Jamali","raw_affiliation_strings":["Department of Electrical Engineering & Computer Science, The University of Toledo, Toledo, OH","Department of Electrical Engineering and Computer Science, The University of Toledo, OH 43606, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Computer Science, The University of Toledo, Toledo, OH","institution_ids":["https://openalex.org/I90871651"]},{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, The University of Toledo, OH 43606, USA","institution_ids":["https://openalex.org/I90871651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110201095","display_name":"Matthew B. Longbrake","orcid":null},"institutions":[{"id":"https://openalex.org/I1280414376","display_name":"United States Air Force Research Laboratory","ror":"https://ror.org/02e2egq70","country_code":"US","type":"facility","lineage":["https://openalex.org/I1280414376","https://openalex.org/I1330347796","https://openalex.org/I4210102105","https://openalex.org/I4389425425"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew B. Longbrake","raw_affiliation_strings":["AFRL/RYDR, Wright-Patterson AFB, Dayton, OH","AFRL/RYDR, Wright-Patterson AFB, Dayton, OH, 45433, USA"],"affiliations":[{"raw_affiliation_string":"AFRL/RYDR, Wright-Patterson AFB, Dayton, OH","institution_ids":["https://openalex.org/I1280414376"]},{"raw_affiliation_string":"AFRL/RYDR, Wright-Patterson AFB, Dayton, OH, 45433, USA","institution_ids":["https://openalex.org/I1280414376"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039059878","display_name":"Peter E. Buxa","orcid":null},"institutions":[{"id":"https://openalex.org/I1280414376","display_name":"United States Air Force Research Laboratory","ror":"https://ror.org/02e2egq70","country_code":"US","type":"facility","lineage":["https://openalex.org/I1280414376","https://openalex.org/I1330347796","https://openalex.org/I4210102105","https://openalex.org/I4389425425"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter E. Buxa","raw_affiliation_strings":["AFRL/RYDR, Wright-Patterson AFB, Dayton, OH","AFRL/RYDR, Wright-Patterson AFB, Dayton, OH, 45433, USA"],"affiliations":[{"raw_affiliation_string":"AFRL/RYDR, Wright-Patterson AFB, Dayton, OH","institution_ids":["https://openalex.org/I1280414376"]},{"raw_affiliation_string":"AFRL/RYDR, Wright-Patterson AFB, Dayton, OH, 45433, USA","institution_ids":["https://openalex.org/I1280414376"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5020618891"],"corresponding_institution_ids":["https://openalex.org/I90871651"],"apc_list":null,"apc_paid":null,"fwci":0.5801,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.64821061,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"237","last_page":"240"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7683550119400024},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7550208568572998},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7417118549346924},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6375051736831665},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5203841924667358},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.5074710249900818},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.48831793665885925},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47570616006851196},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.4569428861141205},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4506703019142151},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.42009490728378296},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37436443567276},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1263657808303833}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7683550119400024},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7550208568572998},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7417118549346924},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6375051736831665},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5203841924667358},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.5074710249900818},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.48831793665885925},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47570616006851196},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.4569428861141205},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4506703019142151},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.42009490728378296},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37436443567276},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1263657808303833},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/newcas.2012.6329000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/newcas.2012.6329000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE International NEWCAS Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2049140806","https://openalex.org/W2061171222","https://openalex.org/W2095874892","https://openalex.org/W2146279773","https://openalex.org/W4243513962","https://openalex.org/W6662953845"],"related_works":["https://openalex.org/W2070693700","https://openalex.org/W1493975478","https://openalex.org/W2055757880","https://openalex.org/W1650414576","https://openalex.org/W2110818533","https://openalex.org/W1888803177","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2079896081","https://openalex.org/W4236123807"],"abstract_inverted_index":{"Hand-coding":[0],"Fast":[1],"Fourier":[2],"Transforms":[3],"(FFTs)":[4],"in":[5,52],"Hardware":[6],"Description":[7],"Language":[8],"(HDL)":[9],"is":[10,33,64,112],"time":[11],"consuming":[12],"and":[13,26,42,73,85,92,119,133],"prone":[14],"to":[15,105,121],"errors.":[16],"Proprietary":[17],"IP":[18],"cores":[19],"are":[20,24,137],"available,":[21,34],"however":[22,35],"they":[23],"closed-source":[25],"unviewable.":[27],"The":[28],"open-source":[29],"FFT":[30,47,71,76,130],"generator":[31],"SPIRAL":[32],"it":[36],"only":[37],"produces":[38],"parallel":[39,90],"arithmetic":[40,91],"solutions":[41],"thus":[43],"limits":[44],"the":[45],"maximum":[46,83],"size":[48],"that":[49,66],"will":[50],"fit":[51,106],"available":[53,108],"Field":[54],"Programmable":[55],"Gate":[56],"Arrays":[57],"(FPGAs).":[58],"An":[59],"autogenerator":[60],"of":[61,70,80],"VHDL":[62],"FFTs":[63,104,118],"described":[65],"takes":[67],"a":[68],"set":[69],"parameters":[72],"generates":[74],"an":[75],"component":[77],"with":[78],"feedback":[79],"occupied":[81],"slices,":[82],"frequency,":[84],"dynamic":[86],"range":[87],"performance.":[88],"Both":[89],"serial-parallel":[93,100,117],"butterfly":[94],"architectures":[95],"can":[96],"be":[97],"generated":[98],"where":[99],"allows":[101],"larger":[102],"sized":[103,116],"inside":[107],"FPGA":[109,134],"parts.":[110],"Emphasis":[111],"placed":[113],"on":[114],"large":[115],"portability":[120],"Application-Specific":[122],"Integrated":[123],"Circuits":[124],"(ASICs)":[125],"using":[126],"Cadence":[127],"Encounter.":[128],"Serial-parallel":[129],"pipeline":[131],"control":[132],"hardware":[135],"reduction":[136],"also":[138],"investigated.":[139]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
