{"id":"https://openalex.org/W2156853082","doi":"https://doi.org/10.1109/nesea.2012.6474022","title":"Logic design of structured configurable controllers","display_name":"Logic design of structured configurable controllers","publication_year":2012,"publication_date":"2012-12-01","ids":{"openalex":"https://openalex.org/W2156853082","doi":"https://doi.org/10.1109/nesea.2012.6474022","mag":"2156853082"},"language":"en","primary_location":{"id":"doi:10.1109/nesea.2012.6474022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nesea.2012.6474022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011398411","display_name":"Jacek Tkacz","orcid":null},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Jacek Tkacz","raw_affiliation_strings":["Institute of Computer Engineering and Electronics, University of Zielona G\u00f3ra, Zielona Gora, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering and Electronics, University of Zielona G\u00f3ra, Zielona Gora, Poland","institution_ids":["https://openalex.org/I46305939"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112277692","display_name":"Marian Adamski","orcid":null},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Marian Adamski","raw_affiliation_strings":["Institute of Computer Engineering and Electronics, University of Zielona G\u00f3ra, Zielona Gora, Poland"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering and Electronics, University of Zielona G\u00f3ra, Zielona Gora, Poland","institution_ids":["https://openalex.org/I46305939"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5011398411"],"corresponding_institution_ids":["https://openalex.org/I46305939"],"apc_list":null,"apc_paid":null,"fwci":3.3696,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.92817919,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"356","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7239939570426941},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7162889242172241},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.7104674577713013},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6473324298858643},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5989097952842712},{"id":"https://openalex.org/keywords/sequent","display_name":"Sequent","score":0.5811247825622559},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4926779866218567},{"id":"https://openalex.org/keywords/sequent-calculus","display_name":"Sequent calculus","score":0.4864218235015869},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.459716796875},{"id":"https://openalex.org/keywords/function-block-diagram","display_name":"Function block diagram","score":0.4536646008491516},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.4401555061340332},{"id":"https://openalex.org/keywords/specification-language","display_name":"Specification language","score":0.43135541677474976},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.421791136264801},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.41583722829818726},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3760722875595093},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.3393019437789917},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.32525867223739624},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2306174337863922},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21506032347679138},{"id":"https://openalex.org/keywords/mathematical-proof","display_name":"Mathematical proof","score":0.1828058958053589},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12916362285614014}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7239939570426941},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7162889242172241},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.7104674577713013},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6473324298858643},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5989097952842712},{"id":"https://openalex.org/C89421646","wikidata":"https://www.wikidata.org/wiki/Q843632","display_name":"Sequent","level":2,"score":0.5811247825622559},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4926779866218567},{"id":"https://openalex.org/C65880906","wikidata":"https://www.wikidata.org/wiki/Q1771121","display_name":"Sequent calculus","level":3,"score":0.4864218235015869},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.459716796875},{"id":"https://openalex.org/C61505648","wikidata":"https://www.wikidata.org/wiki/Q625752","display_name":"Function block diagram","level":3,"score":0.4536646008491516},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.4401555061340332},{"id":"https://openalex.org/C201677973","wikidata":"https://www.wikidata.org/wiki/Q1209840","display_name":"Specification language","level":2,"score":0.43135541677474976},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.421791136264801},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.41583722829818726},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3760722875595093},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.3393019437789917},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.32525867223739624},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2306174337863922},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21506032347679138},{"id":"https://openalex.org/C108710211","wikidata":"https://www.wikidata.org/wiki/Q11538","display_name":"Mathematical proof","level":2,"score":0.1828058958053589},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12916362285614014},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nesea.2012.6474022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nesea.2012.6474022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W925225545","https://openalex.org/W1513458930","https://openalex.org/W1540522725","https://openalex.org/W1844934542","https://openalex.org/W1968486956","https://openalex.org/W2046954130","https://openalex.org/W2086084373","https://openalex.org/W2086723865","https://openalex.org/W2093833684","https://openalex.org/W2135230399","https://openalex.org/W2142340571","https://openalex.org/W2154592611","https://openalex.org/W4236640323","https://openalex.org/W6624629670","https://openalex.org/W6672305408","https://openalex.org/W6674275846"],"related_works":["https://openalex.org/W4253113110","https://openalex.org/W2096191306","https://openalex.org/W2280276996","https://openalex.org/W182117412","https://openalex.org/W1488351281","https://openalex.org/W2138973931","https://openalex.org/W4210342219","https://openalex.org/W93561518","https://openalex.org/W1819006997","https://openalex.org/W3090765541"],"abstract_inverted_index":{"The":[0,14],"paper":[1],"is":[2,17,36],"concentrated":[3],"on":[4],"behavioral":[5],"and":[6,44],"structural":[7],"specification":[8,35],"of":[9,31],"reconfigurable":[10],"logic":[11,33],"controllers":[12],"(RLC).":[13],"initial":[15],"description":[16,58],"given":[18],"as":[19],"a":[20],"hierarchical":[21],"modular":[22],"control":[23],"interpreted":[24],"Petri":[25],"net.":[26],"On":[27],"the":[28,32,56],"abstract":[29],"level":[30],"synthesis":[34,45],"written":[37,54],"in":[38,46,55,62],"propositional":[39],"sequent":[40],"language.":[41],"Rapid":[42],"modeling":[43],"FPGA":[47],"can":[48],"be":[49],"done":[50],"directly":[51],"from":[52],"expressions,":[53],"hardware":[57],"language,":[59],"for":[60],"example":[61],"VHDL.":[63]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}