{"id":"https://openalex.org/W1992777998","doi":"https://doi.org/10.1109/nesea.2010.5678054","title":"A pattern based methodology for the design and implementation of multiplexed Master-Slave devices at the system-level use-case: Modeling a Level-2 Cache IP module at transaction level","display_name":"A pattern based methodology for the design and implementation of multiplexed Master-Slave devices at the system-level use-case: Modeling a Level-2 Cache IP module at transaction level","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W1992777998","doi":"https://doi.org/10.1109/nesea.2010.5678054","mag":"1992777998"},"language":"en","primary_location":{"id":"doi:10.1109/nesea.2010.5678054","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nesea.2010.5678054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Conference on Networked Embedded Systems for Enterprise Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072859158","display_name":"Sushil Menon","orcid":null},"institutions":[{"id":"https://openalex.org/I196608512","display_name":"PES University","ror":"https://ror.org/05m169e78","country_code":"IN","type":"education","lineage":["https://openalex.org/I196608512"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sushil Menon","raw_affiliation_strings":["Centre for System Design & Verification, PES School of Engineering, Bangalore, Karnataka, India","Centre for System Design & Verification, PES School of Engineering, Bangalore-560100, Karnataka, India"],"affiliations":[{"raw_affiliation_string":"Centre for System Design & Verification, PES School of Engineering, Bangalore, Karnataka, India","institution_ids":["https://openalex.org/I196608512"]},{"raw_affiliation_string":"Centre for System Design & Verification, PES School of Engineering, Bangalore-560100, Karnataka, India","institution_ids":["https://openalex.org/I196608512"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090034972","display_name":"Suryaprasad Jayadevappa","orcid":null},"institutions":[{"id":"https://openalex.org/I196608512","display_name":"PES University","ror":"https://ror.org/05m169e78","country_code":"IN","type":"education","lineage":["https://openalex.org/I196608512"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"J. Suryaprasad","raw_affiliation_strings":["Centre for System Design & Verification, PES School of Engineering, Bangalore, Karnataka, India","PES School of Engineering, Bangalore-560100, Karnataka, India"],"affiliations":[{"raw_affiliation_string":"Centre for System Design & Verification, PES School of Engineering, Bangalore, Karnataka, India","institution_ids":["https://openalex.org/I196608512"]},{"raw_affiliation_string":"PES School of Engineering, Bangalore-560100, Karnataka, India","institution_ids":["https://openalex.org/I196608512"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072859158"],"corresponding_institution_ids":["https://openalex.org/I196608512"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10973996,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9854000210762024,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9854000210762024,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9843000173568726,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9829000234603882,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7844982147216797},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7011778354644775},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.6563504934310913},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.5219423174858093},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.49493950605392456},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.463532954454422},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4519387185573578},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4299316108226776},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.26813629269599915},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22975018620491028},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.1685529351234436},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09849834442138672}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7844982147216797},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7011778354644775},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.6563504934310913},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.5219423174858093},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.49493950605392456},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.463532954454422},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4519387185573578},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4299316108226776},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.26813629269599915},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22975018620491028},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.1685529351234436},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09849834442138672}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nesea.2010.5678054","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nesea.2010.5678054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Conference on Networked Embedded Systems for Enterprise Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2167639243","https://openalex.org/W2512056469"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2532163536","https://openalex.org/W1981924702","https://openalex.org/W2069603759","https://openalex.org/W2266880325","https://openalex.org/W2097331811","https://openalex.org/W2533881872","https://openalex.org/W2112120387","https://openalex.org/W2157772069","https://openalex.org/W3146089259"],"abstract_inverted_index":{"In":[0,99,210],"a":[1,7,57,87,118,141,219,242,247,278],"customer":[2],"driven":[3],"environment,":[4],"systems":[5],"pose":[6],"great":[8],"challenge":[9],"to":[10,21,48,85,101,133,139,198,264,277,284],"designers":[11,19],"in":[12,201],"terms":[13],"of":[14,42,50,63,67,72,78,96,151,221,224,268],"complexity":[15],"and":[16,103,125,158,182,207,226,253],"time-to-market.":[17],"Thus,":[18],"have":[20],"look":[22],"at":[23,75,232],"Commercial-Off-The-Shelf":[24],"(COTS)":[25],"based":[26,121],"development":[27],"techniques":[28],"that":[29,80,113,164],"rely":[30],"on":[31],"integrating":[32],"components":[33,43,74],"produced":[34],"by":[35,294],"various":[36,45,68,97],"manufacturers.":[37],"However,":[38],"the":[39,94,110,135,152,188,215,222,235,250,266,269,287],"vast":[40],"range":[41],"from":[44,298],"manufacturers":[46],"leads":[47],"obscurity":[49],"interfaces":[51],"between":[52],"them,":[53],"making":[54],"system":[55,73],"integration":[56],"dreadful":[58],"task.":[59],"Hence,":[60],"large":[61],"warehouses":[62],"IP":[64,105,230],"modules":[65,106],"comprising":[66],"software":[69],"simulation":[70],"models":[71],"different":[76],"levels":[77],"abstraction":[79],"can":[81],"be":[82],"readily":[83],"integrated":[84,174],"form":[86],"Virtual":[88],"Prototype":[89],"are":[90],"highly":[91],"beneficial":[92],"towards":[93],"exploration":[95],"architectures.":[98],"order":[100],"design":[102],"implement":[104,166],"efficiently,":[107],"we":[108,137,165,213],"identify":[109],"Design":[111,119,237],"patterns":[112],"they":[114],"follow.":[115],"We":[116,292],"propose":[117],"pattern":[120],"methodology":[122,217],"for":[123],"modeling":[124,225],"implementing":[126],"multiplexed":[127],"Master-Slave":[128],"devices.":[129],"As":[130],"an":[131,173,228],"effort":[132],"showcase":[134],"methodology,":[136],"choose":[138],"model":[140,171],"Level-2":[142],"Cache":[143],"(L2Cache)":[144],"using":[145,160,167,234],"SystemC.":[146,168],"A":[147],"technical":[148],"specification":[149],"document":[150],"Motorola":[153],"MPC2605":[154],"L2Cache":[155,176,192,202,229,251],"is":[156,172,194,282,289],"procured":[157],"modeled":[159],"hierarchical":[161],"state":[162],"machines":[163],"The":[169,191,239,272],"developed":[170,270],"lookaside":[175],"supporting":[177],"4-way":[178],"set-associative":[179],"cache":[180,204],"mapping":[181,205],"LRU":[183],"replacement":[184,208],"algorithm,":[185],"compatible":[186],"with":[187,301],"Simple":[189,248],"Bus.":[190],"module":[193,231],"then":[195],"further":[196],"parameterized":[197],"accommodate":[199],"changes":[200],"size,":[203],"strategies":[206],"algorithms.":[209],"this":[211,302],"paper,":[212],"present":[214],"proposed":[216],"through":[218],"description":[220],"process":[223],"verifying":[227],"system-level,":[233],"\u201cMaster-Bus-Slave/Master-Bus-Slave\u201d":[236],"pattern.":[238],"test-bench":[240],"involves":[241],"master":[243],"(to":[244],"generate":[245],"transactions),":[246],"Bus,":[249],"Module":[252,255],"Slave":[254],"(Simple":[256],"memory).":[257],"Various":[258],"relevant":[259],"test":[260,265],"cases":[261],"were":[262,275],"generated":[263],"functionality":[267],"module.":[271],"test-case":[273],"outputs":[274],"routed":[276],"debug":[279],"file":[280],"which":[281],"inspected":[283],"determine":[285],"whether":[286],"output":[288],"as":[290],"expected.":[291],"conclude":[293],"enunciating":[295],"our":[296,299],"learning":[297],"experience":[300],"methodology.":[303]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}