{"id":"https://openalex.org/W4410341935","doi":"https://doi.org/10.1109/ncc63735.2025.10983473","title":"High Accuracy Timing Clock Synchronization on RFSoC Board","display_name":"High Accuracy Timing Clock Synchronization on RFSoC Board","publication_year":2025,"publication_date":"2025-03-06","ids":{"openalex":"https://openalex.org/W4410341935","doi":"https://doi.org/10.1109/ncc63735.2025.10983473"},"language":"en","primary_location":{"id":"doi:10.1109/ncc63735.2025.10983473","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ncc63735.2025.10983473","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 National Conference on Communications (NCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101323303","display_name":"Saravana Vilashini M","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Saravana Vilashini M","raw_affiliation_strings":["Indian Institute of Technology Madras,Department of Electrical Engineering,Chennai,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras,Department of Electrical Engineering,Chennai,India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103644523","display_name":"Vaibhav Pratap Singh","orcid":"https://orcid.org/0009-0005-5219-5852"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vaibhav Pratap Singh","raw_affiliation_strings":["Indian Institute of Technology Madras,Department of Electrical Engineering,Chennai,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras,Department of Electrical Engineering,Chennai,India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059634535","display_name":"Anil Prabhakar","orcid":"https://orcid.org/0000-0003-0808-3157"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anil Prabhakar","raw_affiliation_strings":["Indian Institute of Technology Madras,Department of Electrical Engineering,Chennai,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras,Department of Electrical Engineering,Chennai,India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101323303"],"corresponding_institution_ids":["https://openalex.org/I24676775"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10589219,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12216","display_name":"Network Time Synchronization Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.7011620402336121},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.6927160620689392},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6303883194923401},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.48219457268714905},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4346056580543518},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.42094871401786804},{"id":"https://openalex.org/keywords/time-synchronization","display_name":"Time synchronization","score":0.41776689887046814},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29325443506240845},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16063407063484192}],"concepts":[{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.7011620402336121},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.6927160620689392},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6303883194923401},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.48219457268714905},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4346056580543518},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.42094871401786804},{"id":"https://openalex.org/C2986737936","wikidata":"https://www.wikidata.org/wiki/Q1058791","display_name":"Time synchronization","level":2,"score":0.41776689887046814},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29325443506240845},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16063407063484192},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ncc63735.2025.10983473","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ncc63735.2025.10983473","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 National Conference on Communications (NCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1913784304","https://openalex.org/W1990336694","https://openalex.org/W2115333137","https://openalex.org/W2313204139","https://openalex.org/W3009060965","https://openalex.org/W3027661302","https://openalex.org/W3042899737","https://openalex.org/W3217167909","https://openalex.org/W4229846068","https://openalex.org/W4283816174"],"related_works":["https://openalex.org/W2187730212","https://openalex.org/W4312714696","https://openalex.org/W1986532039","https://openalex.org/W2056842641","https://openalex.org/W2356054222","https://openalex.org/W2143367814","https://openalex.org/W2255329889","https://openalex.org/W2390136521","https://openalex.org/W2621832050","https://openalex.org/W1988584558"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"an":[5],"implementation":[6],"of":[7,25,28],"clock":[8],"synchronization":[9],"on":[10,21,62,68],"a":[11,19],"Field":[12],"Programmable":[13],"Gate":[14],"Array":[15],"(FPGA)":[16],"platform,":[17],"with":[18,72],"focus":[20],"achieving":[22],"ultra-low":[23],"jitter":[24],"the":[26,59,73],"order":[27],"50":[29],"picoseconds":[30],"over":[31],"fiber":[32],"optic":[33],"channel":[34],"extending":[35],"up":[36],"to":[37],"80":[38],"km":[39],"without":[40],"amplification.":[41],"We":[42],"also":[43],"demonstrate":[44],"256":[45],"Mbps":[46],"data":[47,60],"transmission":[48],"using":[49],"Quadrature":[50],"Phase":[51],"Shift":[52],"Keying":[53],"(QPSK)":[54],"modulation":[55],"and":[56],"demodulation,":[57],"where":[58],"generated":[61],"one":[63],"FPGA":[64,70],"board":[65,71],"are":[66],"acquired":[67],"another":[69],"synchronized":[74],"clock.":[75]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
