{"id":"https://openalex.org/W2950652883","doi":"https://doi.org/10.1109/ncc.2019.8732236","title":"High Performance Multiplierless Serial Pipelined VLSI Architecture for Real-Valued FFT","display_name":"High Performance Multiplierless Serial Pipelined VLSI Architecture for Real-Valued FFT","publication_year":2019,"publication_date":"2019-02-01","ids":{"openalex":"https://openalex.org/W2950652883","doi":"https://doi.org/10.1109/ncc.2019.8732236","mag":"2950652883"},"language":"en","primary_location":{"id":"doi:10.1109/ncc.2019.8732236","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ncc.2019.8732236","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 National Conference on Communications (NCC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064462505","display_name":"Jinti Hazarika","orcid":"https://orcid.org/0000-0002-0134-6332"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Jinti Hazarika","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013413433","display_name":"Mohd. Tasleem Khan","orcid":"https://orcid.org/0000-0001-6106-1534"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mohd Tasleem Khan","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087714151","display_name":"Shaik Rafi Ahamed","orcid":"https://orcid.org/0000-0003-1617-2299"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shaik Rafi Ahamed","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072118111","display_name":"Harshal B. Nemade","orcid":"https://orcid.org/0000-0002-4792-8979"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Harshal B. Nemade","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati","institution_ids":["https://openalex.org/I1317621060"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5064462505"],"corresponding_institution_ids":["https://openalex.org/I1317621060"],"apc_list":null,"apc_paid":null,"fwci":0.3317,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.5407512,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9869999885559082,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7600886821746826},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6662832498550415},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6244015693664551},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6210676431655884},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5595424771308899},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5497933626174927},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5045057535171509},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5036212801933289},{"id":"https://openalex.org/keywords/twiddle-factor","display_name":"Twiddle factor","score":0.4891119599342346},{"id":"https://openalex.org/keywords/split-radix-fft-algorithm","display_name":"Split-radix FFT algorithm","score":0.4476564824581146},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.44746217131614685},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.41513317823410034},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3590059280395508},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3397766947746277},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29966408014297485},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2775754928588867},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20870810747146606},{"id":"https://openalex.org/keywords/fourier-transform","display_name":"Fourier transform","score":0.1246248185634613},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10189935564994812}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7600886821746826},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6662832498550415},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6244015693664551},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6210676431655884},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5595424771308899},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5497933626174927},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5045057535171509},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5036212801933289},{"id":"https://openalex.org/C4697666","wikidata":"https://www.wikidata.org/wiki/Q7857913","display_name":"Twiddle factor","level":5,"score":0.4891119599342346},{"id":"https://openalex.org/C103755468","wikidata":"https://www.wikidata.org/wiki/Q17103599","display_name":"Split-radix FFT algorithm","level":5,"score":0.4476564824581146},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.44746217131614685},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.41513317823410034},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3590059280395508},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3397766947746277},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29966408014297485},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2775754928588867},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20870810747146606},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.1246248185634613},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10189935564994812},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C203024314","wikidata":"https://www.wikidata.org/wiki/Q1365258","display_name":"Fourier analysis","level":3,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C166386157","wikidata":"https://www.wikidata.org/wiki/Q1477735","display_name":"Short-time Fourier transform","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ncc.2019.8732236","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ncc.2019.8732236","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 National Conference on Communications (NCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1567503803","https://openalex.org/W1591661045","https://openalex.org/W1985295496","https://openalex.org/W2035137327","https://openalex.org/W2065490696","https://openalex.org/W2104176873","https://openalex.org/W2119329660","https://openalex.org/W2151743818","https://openalex.org/W2317906089","https://openalex.org/W2324524642","https://openalex.org/W2756095346","https://openalex.org/W2890379003","https://openalex.org/W6675859611","https://openalex.org/W6744179189","https://openalex.org/W6754518812"],"related_works":["https://openalex.org/W2031343199","https://openalex.org/W1984254719","https://openalex.org/W2017578039","https://openalex.org/W4229456379","https://openalex.org/W2351401773","https://openalex.org/W2371538653","https://openalex.org/W2151986570","https://openalex.org/W2061302196","https://openalex.org/W2394044501","https://openalex.org/W1503228241"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,43],"high-performance":[4],"multiplierless":[5,65],"serial":[6,26],"pipelined":[7,27],"architecture":[8],"for":[9,23,133],"real-valued":[10],"fast":[11],"Fourier":[12],"transform":[13],"(FFT).":[14],"A":[15],"new":[16],"data":[17],"mapping":[18],"scheme":[19],"(DMS)":[20],"is":[21,32,49,60],"suggested":[22],"the":[24,50,86,99,103,107,130,161],"proposed":[25,104,131],"FFT":[28,36],"architecture.":[29],"The":[30,77],"performance":[31,59],"enhanced":[33],"by":[34,42,62,93,114],"performing":[35],"computations":[37],"in":[38,54,58,74],"log2N-1":[39],"stages":[40],"followed":[41],"select-store-feedback":[44],"(SSF)":[45],"stage,":[46],"where":[47],"N":[48],"number":[51,81],"of":[52,69,82],"points":[53],"FFT.":[55],"Further":[56],"enhancement":[57],"achieved":[61],"employing":[63],"quarter-complex":[64],"unit":[66],"made":[67],"up":[68],"memory":[70,78],"and":[71,121,153],"combinational":[72,95],"logic":[73],"every":[75],"stage.":[76],"stores":[79],"half":[80],"partial":[83,88],"products":[84,89],"while":[85],"remaining":[87],"are":[90],"taken":[91],"care":[92],"external":[94],"logic.":[96],"Compared":[97],"with":[98],"best":[100,162],"existing":[101,163],"scheme,":[102],"design":[105,132],"reduces":[106],"computational":[108],"workload":[109],"on":[110],"half-butterfly":[111],"(H-BF)":[112],"units":[113],"(2N-8).":[115],"Application":[116],"specific":[117],"integrated":[118],"circuit":[119],"(ASIC)":[120],"field":[122],"programmable":[123],"gate":[124],"array":[125],"(FPGA)":[126],"results":[127],"show":[128],"that":[129],"1024-point":[134],"achieves":[135],"31.54%":[136],"less":[137,140,143,148,155],"area,":[138],"30.13%":[139],"power,":[141],"33.56%":[142],"area-delay":[144],"product":[145],"(ADP),":[146],"27.11%":[147],"sliced":[149],"look-up":[150],"tables":[151],"(SLUTs)":[152],"28.37%":[154],"flip-flops":[156],"(FFs)":[157],"as":[158],"compared":[159],"to":[160],"scheme.":[164]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}