{"id":"https://openalex.org/W2510504684","doi":"https://doi.org/10.1109/nas.2016.7549417","title":"Reducing Read Latency in MLC PCM","display_name":"Reducing Read Latency in MLC PCM","publication_year":2016,"publication_date":"2016-08-01","ids":{"openalex":"https://openalex.org/W2510504684","doi":"https://doi.org/10.1109/nas.2016.7549417","mag":"2510504684"},"language":"en","primary_location":{"id":"doi:10.1109/nas.2016.7549417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nas.2016.7549417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Networking, Architecture and Storage (NAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070528368","display_name":"Jianhui Yue","orcid":"https://orcid.org/0000-0002-1876-6931"},"institutions":[{"id":"https://openalex.org/I83328450","display_name":"Miami University","ror":"https://ror.org/05nbqxr67","country_code":"US","type":"education","lineage":["https://openalex.org/I83328450"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jianhui Yue","raw_affiliation_strings":["Dept. of Computer Science & Software Engineering, Miami University, Oxford, OH"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science & Software Engineering, Miami University, Oxford, OH","institution_ids":["https://openalex.org/I83328450"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102214085","display_name":"Yifeng Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I7947594","display_name":"University of Maine","ror":"https://ror.org/01adr0w49","country_code":"US","type":"education","lineage":["https://openalex.org/I2802397601","https://openalex.org/I7947594"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yifeng Zhu","raw_affiliation_strings":["Dept. of Elec. & Computer, University of Maine, Orono, ME"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Elec. & Computer, University of Maine, Orono, ME","institution_ids":["https://openalex.org/I7947594"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2241,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.38037291,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8292567729949951},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.7250807285308838},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6813690662384033},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6164606213569641},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.571489155292511},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5006940364837646},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46277984976768494},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37852638959884644},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.18950119614601135},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.07974845170974731}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8292567729949951},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.7250807285308838},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6813690662384033},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6164606213569641},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.571489155292511},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5006940364837646},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46277984976768494},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37852638959884644},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.18950119614601135},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.07974845170974731},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nas.2016.7549417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nas.2016.7549417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Networking, Architecture and Storage (NAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W1555915743","https://openalex.org/W1983826793","https://openalex.org/W1993099545","https://openalex.org/W1996288726","https://openalex.org/W2000270805","https://openalex.org/W2036934942","https://openalex.org/W2041420601","https://openalex.org/W2041588416","https://openalex.org/W2055818721","https://openalex.org/W2082070657","https://openalex.org/W2096259250","https://openalex.org/W2097823832","https://openalex.org/W2102449048","https://openalex.org/W2108534683","https://openalex.org/W2123728009","https://openalex.org/W2124165274","https://openalex.org/W2124632665","https://openalex.org/W2147657366","https://openalex.org/W2159862818","https://openalex.org/W4237860043","https://openalex.org/W4240569795","https://openalex.org/W4250969878","https://openalex.org/W4253877280","https://openalex.org/W6671183045","https://openalex.org/W6674323626"],"related_works":["https://openalex.org/W2167303720","https://openalex.org/W2133682266","https://openalex.org/W2497617944","https://openalex.org/W1563139915","https://openalex.org/W2109715593","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W2268996566","https://openalex.org/W4256652509","https://openalex.org/W2140219379"],"abstract_inverted_index":{"Multi-level-cell":[0],"(MLC)":[1],"phase-change":[2],"memory":[3,155],"(PCM)":[4],"provides":[5],"higher":[6],"storage":[7],"density":[8],"at":[9,66,86,96,128],"the":[10,67,79,93,102,111,122,129],"cost":[11],"of":[12,48,52,55,82,89,114,201],"slower":[13],"reads":[14,18,42],"and":[15,27,58,92,160,183,206],"writes.":[16],"Since":[17],"are":[19,108],"latency":[20,157,182,200],"critical,":[21],"this":[22],"paper":[23],"propose":[24],"a":[25,60,115,119],"simple":[26],"effective":[28],"bit":[29,68,72],"mapping":[30],"scheme,":[31],"called":[32],"Mapping":[33],"Critical":[34],"Word":[35],"to":[36,39,193],"MSBs":[37],"(MCWM),":[38],"address":[40],"slow":[41],"in":[43,181,185],"MLC.":[44],"MCWM":[45,77,152,172,190,196],"takes":[46],"advantage":[47],"fast":[49],"read":[50,156,199],"speed":[51,131],"most-significant-bits":[53,87],"(MSBs)":[54,88],"MLC":[56,64,73,90],"cells":[57,65],"strips":[59],"cache":[61,84,116,120],"line":[62,85],"among":[63],"level.":[69],"Taking":[70],"2-":[71],"as":[74,132],"an":[75],"example,":[76],"stores":[78],"first":[80,112],"half":[81,95,113],"each":[83],"cells,":[91],"second":[94],"least-significant-bits":[97],"(LSBs).":[98],"This":[99],"design":[100],"leverages":[101],"observation":[103],"that":[104,151],"most":[105],"critical":[106,123],"words":[107],"located":[109],"within":[110],"line.":[117],"Upon":[118],"miss,":[121],"word":[124],"can":[125,153,197],"be":[126],"fetched":[127],"same":[130],"single-level":[133],"cell":[134],"(SLC)":[135],"PCM,":[136],"thus":[137],"reducing":[138],"processor":[139],"stall":[140],"time.":[141],"Experimental":[142],"results":[143],"under":[144],"4-cores":[145],"SPEC":[146],"CPU":[147],"2006":[148],"workloads":[149],"show":[150],"reduce":[154,198],"by":[158,162,179,204,209],"27.5%":[159],"IPC":[161,186,208],"13.7%":[163],"on":[164,187,211],"average,":[165],"compared":[166],"with":[167],"conventional":[168],"PCM.":[169],"In":[170],"addition,":[171],"outperforms":[173],"recently":[174],"proposed":[175],"Striped":[176],"PCM":[177],"(SPCM)":[178],"12.5%":[180],"6.1%":[184],"average.":[188,212],"Additionally,":[189],"is":[191],"complementary":[192],"write":[194],"optimizations.":[195],"Write":[202],"Pause":[203],"25%":[205],"increase":[207],"11.7%":[210]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}