{"id":"https://openalex.org/W2758268299","doi":"https://doi.org/10.1109/nanoarch.2017.8053715","title":"Linear regression based multi-state logic decomposition approach for efficient hardware implementation","display_name":"Linear regression based multi-state logic decomposition approach for efficient hardware implementation","publication_year":2017,"publication_date":"2017-07-01","ids":{"openalex":"https://openalex.org/W2758268299","doi":"https://doi.org/10.1109/nanoarch.2017.8053715","mag":"2758268299"},"language":"en","primary_location":{"id":"doi:10.1109/nanoarch.2017.8053715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nanoarch.2017.8053715","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085471982","display_name":"Wafi Danesh","orcid":"https://orcid.org/0000-0001-8162-9158"},"institutions":[{"id":"https://openalex.org/I75421653","display_name":"University of Missouri\u2013Kansas City","ror":"https://ror.org/01w0d5g70","country_code":"US","type":"education","lineage":["https://openalex.org/I75421653"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wafi Danesh","raw_affiliation_strings":["Computer Science and Electrical Engineering Department, University of Missouri Kansas City, Kansas City, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Electrical Engineering Department, University of Missouri Kansas City, Kansas City, USA","institution_ids":["https://openalex.org/I75421653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052808482","display_name":"Mostafizur Rahman","orcid":"https://orcid.org/0000-0002-7318-3528"},"institutions":[{"id":"https://openalex.org/I75421653","display_name":"University of Missouri\u2013Kansas City","ror":"https://ror.org/01w0d5g70","country_code":"US","type":"education","lineage":["https://openalex.org/I75421653"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mostafizur Rahman","raw_affiliation_strings":["Computer Science and Electrical Engineering Department, University of Missouri Kansas City, Kansas City, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Electrical Engineering Department, University of Missouri Kansas City, Kansas City, USA","institution_ids":["https://openalex.org/I75421653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5085471982"],"corresponding_institution_ids":["https://openalex.org/I75421653"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.122719,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"654","issue":null,"first_page":"153","last_page":"154"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6683289408683777},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6322826147079468},{"id":"https://openalex.org/keywords/nanoelectronics","display_name":"Nanoelectronics","score":0.6106627583503723},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6100526452064514},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5885159969329834},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5735577940940857},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5545262694358826},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5042725801467896},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4842807650566101},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4399825632572174},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4372400641441345},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.41690096259117126},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.415547251701355},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.37296074628829956},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2405436933040619},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19757488369941711},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13167735934257507},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.09330254793167114},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.0849657654762268}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6683289408683777},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6322826147079468},{"id":"https://openalex.org/C141400236","wikidata":"https://www.wikidata.org/wiki/Q1479544","display_name":"Nanoelectronics","level":2,"score":0.6106627583503723},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6100526452064514},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5885159969329834},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5735577940940857},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5545262694358826},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5042725801467896},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4842807650566101},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4399825632572174},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4372400641441345},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.41690096259117126},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.415547251701355},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.37296074628829956},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2405436933040619},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19757488369941711},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13167735934257507},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.09330254793167114},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0849657654762268}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nanoarch.2017.8053715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nanoarch.2017.8053715","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1578592046","https://openalex.org/W1972333022","https://openalex.org/W2034814119","https://openalex.org/W2294839272","https://openalex.org/W2495240296","https://openalex.org/W4211219479"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2082591327","https://openalex.org/W2066518505","https://openalex.org/W2167525841","https://openalex.org/W2991771859","https://openalex.org/W2619968078","https://openalex.org/W1529529399","https://openalex.org/W1977171228","https://openalex.org/W2121963733","https://openalex.org/W2103473573"],"abstract_inverted_index":{"The":[0],"following":[1],"topics":[2],"are":[3],"dealt":[4],"with:":[5],"memory":[6],"architecture;":[7],"MRAM":[8],"devices;":[9],"logic":[10,15,24],"gates;":[11],"low-power":[12],"electronics;":[13],"CMOS":[14],"circuits;":[16,20],"nanowires;":[17],"three-dimensional":[18],"integrated":[19],"magnetoelectronics;":[21],"nanoelectronics;":[22],"and":[23],"design.":[25]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
