{"id":"https://openalex.org/W2130950448","doi":"https://doi.org/10.1109/nanoarch.2007.4400852","title":"A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions","display_name":"A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions","publication_year":2007,"publication_date":"2007-10-01","ids":{"openalex":"https://openalex.org/W2130950448","doi":"https://doi.org/10.1109/nanoarch.2007.4400852","mag":"2130950448"},"language":"en","primary_location":{"id":"doi:10.1109/nanoarch.2007.4400852","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nanoarch.2007.4400852","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Symposium on Nanoscale Architectures","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060198895","display_name":"Ashish Kumar Singh","orcid":"https://orcid.org/0000-0003-3856-2896"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ashish Singh","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, Austin, USA","Department of Electrical and Computer Engineering, University of Texas at Austin, , USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, , USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008811609","display_name":"Hady Zeineddine","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hady Ali Zeineddine","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, Austin, USA","Department of Electrical and Computer Engineering, University of Texas at Austin, , USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, , USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112689277","display_name":"Adnan Aziz","orcid":"https://orcid.org/0009-0003-5855-6861"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Adnan Aziz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, Austin, USA","Department of Electrical and Computer Engineering, University of Texas at Austin, , USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, , USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088120102","display_name":"Sriram Vishwanath","orcid":"https://orcid.org/0000-0003-3112-4885"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sriram Vishwanath","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, Austin, USA","Department of Electrical and Computer Engineering, University of Texas at Austin, , USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, , USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090899796","display_name":"Michael Orshansky","orcid":"https://orcid.org/0000-0002-6223-4748"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Orshansky","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas, Austin, USA","Department of Electrical and Computer Engineering, University of Texas at Austin, , USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas, Austin, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, , USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5060198895"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":2.8099,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.90653268,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"15","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6986961364746094},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.6872794032096863},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.586050271987915},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.548466145992279},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5081667900085449},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.494052916765213},{"id":"https://openalex.org/keywords/maximum-satisfiability-problem","display_name":"Maximum satisfiability problem","score":0.47749635577201843},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4505428075790405},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.443217009305954},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42260050773620605},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4078766405582428},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.394788920879364},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3910021185874939},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38892894983291626},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.18267285823822021},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17668616771697998},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09319812059402466}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6986961364746094},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.6872794032096863},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.586050271987915},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.548466145992279},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5081667900085449},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.494052916765213},{"id":"https://openalex.org/C111797529","wikidata":"https://www.wikidata.org/wiki/Q17080584","display_name":"Maximum satisfiability problem","level":3,"score":0.47749635577201843},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4505428075790405},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.443217009305954},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42260050773620605},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4078766405582428},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.394788920879364},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3910021185874939},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38892894983291626},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.18267285823822021},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17668616771697998},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09319812059402466},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/nanoarch.2007.4400852","is_oa":false,"landing_page_url":"https://doi.org/10.1109/nanoarch.2007.4400852","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Symposium on Nanoscale Architectures","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W60124900","https://openalex.org/W1501488688","https://openalex.org/W1518705996","https://openalex.org/W2050850659","https://openalex.org/W2087364765","https://openalex.org/W2095698047","https://openalex.org/W2107895817","https://openalex.org/W2129183345","https://openalex.org/W2133527541","https://openalex.org/W2137249916","https://openalex.org/W2153551298","https://openalex.org/W2942537621","https://openalex.org/W3000162811","https://openalex.org/W3149732203","https://openalex.org/W3169111758","https://openalex.org/W4236218105","https://openalex.org/W4255371118","https://openalex.org/W6602468283","https://openalex.org/W6796564892"],"related_works":["https://openalex.org/W4288044863","https://openalex.org/W1564702418","https://openalex.org/W3141532631","https://openalex.org/W2724189404","https://openalex.org/W2131164334","https://openalex.org/W1501085929","https://openalex.org/W2296737955","https://openalex.org/W2504025942","https://openalex.org/W1995176744","https://openalex.org/W2080423274"],"abstract_inverted_index":{"We":[0,25,120,128,161,184],"address":[1],"the":[2,69,73,98,139,197],"challenge":[3],"of":[4,8,33,46,75,92,101,135,144,180,190],"implementing":[5],"reliable":[6,39],"computation":[7],"Boolean":[9,76,93,102,107],"functions":[10,103],"in":[11,105,142,178],"future":[12],"nanocircuit":[13],"fabrics.":[14],"Such":[15],"fabrics":[16],"are":[17],"projected":[18],"to":[19,132,159],"have":[20],"very":[21],"high":[22],"defect":[23,60,84,182],"rates.":[24,183],"overcome":[26],"this":[27,47],"limitation":[28],"by":[29,152,164],"using":[30],"a":[31,89,124,171,186],"combination":[32],"cheap":[34],"but":[35,40],"unreliable":[36],"nanodevices":[37],"and":[38,154,196,206],"expensive":[41],"CMOS":[42,204],"devices.":[43],"The":[44,114],"contribution":[45],"work":[48],"is":[49,86,118,176,199],"twofold":[50],"-":[51],"(1)":[52],"A":[53,63],"heterogeneous":[54],"architecture":[55],"suitable":[56],"for":[57,68,78,110,194],"low":[58],"level":[59],"tolerance":[61,85],"(2)":[62],"novel":[64,90],"coding":[65,91,116,137,140,167,214],"strategy":[66],"that":[67,130,163],"first":[70],"time":[71],"exploited":[72],"structure":[74],"function":[77],"better":[79,112],"coder.":[80],"In":[81],"our":[82],"approach,":[83],"achieved":[87],"through":[88],"functions;":[94],"specifically,":[95],"we":[96],"exploit":[97],"don\u2019t":[99],"cares":[100],"encountered":[104],"multi-level":[106],"logic":[108],"networks":[109],"constructing":[111],"codes.":[113],"optimal":[115],"problem":[117],"NPhard.":[119],"solved":[121],"it":[122],"with":[123],"SAT":[125],"based":[126],"heuristic.":[127],"show":[129],"compared":[131,202],"direct":[133],"application":[134],"existing":[136],"techniques,":[138],"overhead":[141],"terms":[143],"extra":[145],"bits":[146],"can":[147,156],"be":[148],"reduced,":[149],"on":[150],"average":[151,173],"23%,":[153],"savings":[155],"go":[157],"up":[158],"34%.":[160],"demonstrate":[162],"incorporating":[165],"efficient":[166],"techniques":[168],"more":[169],"than":[170,192,209],"20%":[172],"yield":[174],"improvement":[175],"possible":[177],"case":[179],"10%":[181],"incur":[185],"negligible":[187],"delay":[188],"penalty":[189],"less":[191],"1%":[193],"decoder":[195],"area":[198],"13X":[200],"smaller":[201,208],"22nm":[203],"technology":[205],"32%":[207],"TMR":[210],"(triple":[211],"modular":[212],"redundancy)":[213],"scheme.":[215]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}