{"id":"https://openalex.org/W4402753594","doi":"https://doi.org/10.1109/mwscas60917.2024.10658870","title":"Memristive-Based Full Adder","display_name":"Memristive-Based Full Adder","publication_year":2024,"publication_date":"2024-08-11","ids":{"openalex":"https://openalex.org/W4402753594","doi":"https://doi.org/10.1109/mwscas60917.2024.10658870"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas60917.2024.10658870","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mwscas60917.2024.10658870","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020110908","display_name":"Khalid Alammari","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Khalid Alammari","raw_affiliation_strings":["University of Windsor,Department of Electrical and Computer Engineering,Windsor,Canada"],"affiliations":[{"raw_affiliation_string":"University of Windsor,Department of Electrical and Computer Engineering,Windsor,Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5116239815","display_name":"Majid Ahmadi","orcid":"https://orcid.org/0009-0006-4046-2121"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Majid Ahmadi","raw_affiliation_strings":["University of Windsor,Department of Electrical and Computer Engineering,Windsor,Canada"],"affiliations":[{"raw_affiliation_string":"University of Windsor,Department of Electrical and Computer Engineering,Windsor,Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100833525","display_name":"Arash Ahmadi","orcid":"https://orcid.org/0000-0001-5094-5967"},"institutions":[{"id":"https://openalex.org/I67031392","display_name":"Carleton University","ror":"https://ror.org/02qtvee93","country_code":"CA","type":"education","lineage":["https://openalex.org/I67031392"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Arash Ahmadi","raw_affiliation_strings":["Carleton University,Department of Electronic,Ottawa,Canada"],"affiliations":[{"raw_affiliation_string":"Carleton University,Department of Electronic,Ottawa,Canada","institution_ids":["https://openalex.org/I67031392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5020110908"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":0.222,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.53048785,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"25","last_page":"28"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12236","display_name":"Photoreceptor and optogenetics research","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8029528260231018},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6646521091461182},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3458082675933838},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12513116002082825}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8029528260231018},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6646521091461182},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3458082675933838},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12513116002082825},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas60917.2024.10658870","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mwscas60917.2024.10658870","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W845285418","https://openalex.org/W1578783943","https://openalex.org/W1977492474","https://openalex.org/W2004782555","https://openalex.org/W2066280488","https://openalex.org/W2081729575","https://openalex.org/W2083537989","https://openalex.org/W2112181056","https://openalex.org/W2162651880","https://openalex.org/W2248506981","https://openalex.org/W2407339173","https://openalex.org/W2516467421","https://openalex.org/W2522667948","https://openalex.org/W2547440906","https://openalex.org/W2569842290","https://openalex.org/W2700200092","https://openalex.org/W2778935320","https://openalex.org/W2793101555","https://openalex.org/W3117291443","https://openalex.org/W4327738655","https://openalex.org/W6623449936"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W1993041309"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,8,24,33],"Memristor-based":[4],"logic":[5],"design":[6,69],"for":[7],"full":[9,21,40],"adder":[10,22,41],"circuit":[11,27],"is":[12,23,42],"proposed,":[13],"utilizing":[14],"MAGIC":[15],"and":[16,48,59],"MRL":[17],"methods.":[18],"The":[19,54,64],"MAGIC-based":[20],"memristor-only":[25],"based":[26],"with":[28,44],"25":[29],"memristors":[30,46],"mapped":[31],"into":[32],"memristive":[34],"crossbar":[35],"structure,":[36],"while":[37],"the":[38,68],"MRL-based":[39],"implemented":[43,58],"18":[45],"devices":[47],"4":[49],"MOSFETs":[50],"in":[51,61],"CMOS-Memristor":[52],"platform.":[53],"proposed":[55],"designs":[56],"were":[57],"simulated":[60],"Cadence":[62],"Virtuoso.":[63],"simulation":[65],"results":[66],"demonstrate":[67],"functionality.":[70]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-12-21T23:12:01.093139","created_date":"2025-10-10T00:00:00"}