{"id":"https://openalex.org/W4391381952","doi":"https://doi.org/10.1109/mwscas57524.2023.10405974","title":"Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface","display_name":"Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface","publication_year":2023,"publication_date":"2023-08-06","ids":{"openalex":"https://openalex.org/W4391381952","doi":"https://doi.org/10.1109/mwscas57524.2023.10405974"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas57524.2023.10405974","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mwscas57524.2023.10405974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045635010","display_name":"Ping Lu","orcid":"https://orcid.org/0000-0002-0111-0573"},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ping Lu","raw_affiliation_strings":["Microsoft Corporate,Morrisville,NC,USA,27560"],"affiliations":[{"raw_affiliation_string":"Microsoft Corporate,Morrisville,NC,USA,27560","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048479935","display_name":"Bupesh Pandita","orcid":null},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bupesh Pandita","raw_affiliation_strings":["Microsoft Corporate,Morrisville,NC,USA,27560"],"affiliations":[{"raw_affiliation_string":"Microsoft Corporate,Morrisville,NC,USA,27560","institution_ids":["https://openalex.org/I1290206253"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070368708","display_name":"Minhan Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1290206253","display_name":"Microsoft (United States)","ror":"https://ror.org/00d0nc645","country_code":"US","type":"company","lineage":["https://openalex.org/I1290206253"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Minhan Chen","raw_affiliation_strings":["Microsoft Corporate,Morrisville,NC,USA,27560"],"affiliations":[{"raw_affiliation_string":"Microsoft Corporate,Morrisville,NC,USA,27560","institution_ids":["https://openalex.org/I1290206253"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5045635010"],"corresponding_institution_ids":["https://openalex.org/I1290206253"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18788285,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"614","last_page":"618"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9212645292282104},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.7687832117080688},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.711830735206604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5966757535934448},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4561462104320526},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.418856143951416},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4017290771007538},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2211761772632599},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11143520474433899}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9212645292282104},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.7687832117080688},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.711830735206604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5966757535934448},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4561462104320526},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.418856143951416},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4017290771007538},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2211761772632599},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11143520474433899},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas57524.2023.10405974","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mwscas57524.2023.10405974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1544882865","https://openalex.org/W2062952706","https://openalex.org/W2163630970","https://openalex.org/W2180973527","https://openalex.org/W2208671480","https://openalex.org/W6688264594"],"related_works":["https://openalex.org/W1488060887","https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W1994021281","https://openalex.org/W2103754166","https://openalex.org/W2043945969","https://openalex.org/W2139484866","https://openalex.org/W2082469970","https://openalex.org/W2058003010"],"abstract_inverted_index":{"An":[0],"accurate":[1],"loop":[2,9],"bandwidth":[3],"(LBW)":[4],"calibration/control":[5],"for":[6],"digital":[7,37],"phase-locked":[8],"(DPLL)":[10],"by":[11,78],"leveraging":[12],"two-point":[13],"injection":[14],"and":[15,35,43,81],"least":[16],"mean":[17],"square":[18],"(LMS)":[19],"algorithm":[20],"is":[21,62],"described":[22],"in":[23,49,84],"this":[24],"work.":[25],"The":[26],"proposed":[27],"method":[28],"does":[29],"not":[30],"need":[31],"any":[32],"external":[33],"stimulus":[34],"complicated":[36],"multipliers,":[38],"which":[39],"simplifies":[40],"the":[41,65,70,90],"circuit":[42],"saves":[44],"chip":[45],"area.":[46],"Being":[47],"used":[48],"a":[50,73,85,95],"multiple-link":[51],"die-to-die":[52],"interface":[53],"where":[54],"two":[55],"or":[56],"more":[57],"common-referenced":[58],"PLLs'":[59],"relative":[60],"jitter":[61,104],"under":[63],"consideration,":[64],"work":[66],"can":[67],"significantly":[68],"mitigate":[69],"impact":[71],"from":[72],"dirty":[74],"reference":[75],"clock.":[76],"Simulated":[77],"combining":[79],"transistor-based":[80],"gate-level":[82],"circuits":[83],"DPLL":[86],"running":[87],"at":[88],"l0GHz,":[89],"calibration":[91],"helps":[92],"to":[93],"achieve":[94],"LBW":[96],"of":[97,107],"~20MHz":[98],"with":[99],"an":[100],"error":[101],"<1.5%":[102],"(reference":[103],"suppression":[105],"factor":[106],"~23dB).":[108]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
