{"id":"https://openalex.org/W4391382037","doi":"https://doi.org/10.1109/mwscas57524.2023.10405908","title":"Electrical and Physical Evaluation of Logic Network Generation Methods for SCCG","display_name":"Electrical and Physical Evaluation of Logic Network Generation Methods for SCCG","publication_year":2023,"publication_date":"2023-08-06","ids":{"openalex":"https://openalex.org/W4391382037","doi":"https://doi.org/10.1109/mwscas57524.2023.10405908"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas57524.2023.10405908","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mwscas57524.2023.10405908","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101298865","display_name":"Jair P\u00e9rez Ram\u00edrez","orcid":null},"institutions":[{"id":"https://openalex.org/I65285256","display_name":"Pontifical Catholic University of Peru","ror":"https://ror.org/00013q465","country_code":"PE","type":"education","lineage":["https://openalex.org/I65285256"]}],"countries":["PE"],"is_corresponding":true,"raw_author_name":"Jair P\u00e9rez Ram\u00edrez","raw_affiliation_strings":["Pontificia Universidad Católica del Perú,Faculty of Science and Engineering,Lima,Perú"],"affiliations":[{"raw_affiliation_string":"Pontificia Universidad Católica del Perú,Faculty of Science and Engineering,Lima,Perú","institution_ids":["https://openalex.org/I65285256"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002002590","display_name":"Carlos Silva-C\u00e1rdenas","orcid":"https://orcid.org/0000-0003-4653-0915"},"institutions":[{"id":"https://openalex.org/I65285256","display_name":"Pontifical Catholic University of Peru","ror":"https://ror.org/00013q465","country_code":"PE","type":"education","lineage":["https://openalex.org/I65285256"]}],"countries":["PE"],"is_corresponding":false,"raw_author_name":"Carlos Silva C\u00e1rdenas","raw_affiliation_strings":["Pontificia Universidad Católica del Perú,Engineering Department,Lima,Perú"],"affiliations":[{"raw_affiliation_string":"Pontificia Universidad Católica del Perú,Engineering Department,Lima,Perú","institution_ids":["https://openalex.org/I65285256"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101298865"],"corresponding_institution_ids":["https://openalex.org/I65285256"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18791985,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"147","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8694228529930115},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7454010844230652},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.7393268942832947},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.6068814396858215},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5852562785148621},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5831639170646667},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5777596831321716},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5649846792221069},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5473393201828003},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.5439008474349976},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5260648131370544},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5068054795265198},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5001671314239502},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.466992050409317},{"id":"https://openalex.org/keywords/microelectronics","display_name":"Microelectronics","score":0.44805407524108887},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4312686324119568},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.424422025680542},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.4225029945373535},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.39918065071105957},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.38632047176361084},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3661673367023468},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3006613850593567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2709123194217682},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.23807919025421143},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2043989896774292},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.18212959170341492},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09074386954307556}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8694228529930115},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7454010844230652},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.7393268942832947},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.6068814396858215},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5852562785148621},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5831639170646667},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5777596831321716},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5649846792221069},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5473393201828003},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.5439008474349976},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5260648131370544},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5068054795265198},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5001671314239502},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.466992050409317},{"id":"https://openalex.org/C187937830","wikidata":"https://www.wikidata.org/wiki/Q175403","display_name":"Microelectronics","level":2,"score":0.44805407524108887},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4312686324119568},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.424422025680542},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.4225029945373535},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.39918065071105957},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.38632047176361084},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3661673367023468},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3006613850593567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2709123194217682},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.23807919025421143},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2043989896774292},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.18212959170341492},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09074386954307556},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas57524.2023.10405908","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/mwscas57524.2023.10405908","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5400000214576721,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1972270843","https://openalex.org/W1979604948","https://openalex.org/W2000038726","https://openalex.org/W2015987974","https://openalex.org/W2018989845","https://openalex.org/W2116118782","https://openalex.org/W2144613608","https://openalex.org/W2263028302","https://openalex.org/W2908417499","https://openalex.org/W2941700911","https://openalex.org/W2993028905","https://openalex.org/W4225349666"],"related_works":["https://openalex.org/W2150722449","https://openalex.org/W4238891425","https://openalex.org/W2173109281","https://openalex.org/W4253343649","https://openalex.org/W2032444288","https://openalex.org/W162881505","https://openalex.org/W2144148526","https://openalex.org/W2993028905","https://openalex.org/W2547075873","https://openalex.org/W4387146044"],"abstract_inverted_index":{"The":[0,114],"digital":[1],"integrated":[2,34],"circuit":[3,35],"implementation":[4],"strategies":[5],"in":[6],"the":[7,13,16,33,42,70,87,118,122,131,137],"microelectronics":[8],"industry":[9],"have":[10,22,57],"changed":[11],"over":[12],"years":[14],"considering":[15],"design":[17,20,36],"costs.":[18],"Hand":[19],"flows":[21],"been":[23],"replaced":[24],"by":[25],"Electronic":[26],"Design":[27],"Automation":[28],"(EDA)":[29],"tools":[30],"that":[31,68,117],"automate":[32],"process.":[37],"However,":[38],"implementing":[39],"ICs":[40],"through":[41],"traditional":[43],"standard":[44],"cell":[45,55],"flow":[46,128],"does":[47],"not":[48],"ensure":[49],"power":[50,99,141],"and":[51,81,96,105,145],"area":[52],"optimization":[53,92],"because":[54],"libraries":[56],"a":[58,126],"limited":[59],"number":[60,101,138],"of":[61,89,102,139],"logical":[62],"functions.":[63],"Therefore,":[64],"research":[65],"has":[66],"shown":[67],"using":[69,130],"Static":[71],"CMOS":[72,111],"Complex":[73],"Gates":[74],"(SCCG)":[75],"approach":[76],"can":[77],"lead":[78],"to":[79,109],"electrical":[80],"physical":[82],"improvements.":[83],"This":[84],"paper":[85],"investigates":[86],"impact":[88],"three":[90],"netlist":[91],"methodologies":[93],"(FAC,":[94],"FAC-PD,":[95],"BDD)":[97],"on":[98],"dissipation,":[100],"transistors,":[103,140],"area,":[104,144],"wirelength":[106],"when":[107,129],"applied":[108],"180nm":[110],"TSMC":[112],"technology.":[113],"study":[115],"shows":[116],"FAC":[119],"method":[120],"is":[121],"most":[123],"suitable":[124],"for":[125],"design-on-the-fly":[127],"SwitchCraft":[132],"framework":[133],"since":[134],"it":[135],"optimizes":[136],"consumption,":[142],"layout":[143],"wirelength,":[146]},"counts_by_year":[],"updated_date":"2025-12-25T23:11:45.687758","created_date":"2025-10-10T00:00:00"}