{"id":"https://openalex.org/W4292873301","doi":"https://doi.org/10.1109/mwscas54063.2022.9859268","title":"A Low-Overhead PUF Based Hardware Security Technique to Prevent Scan Chain Attacks for Industry-Standard DFT Architecture","display_name":"A Low-Overhead PUF Based Hardware Security Technique to Prevent Scan Chain Attacks for Industry-Standard DFT Architecture","publication_year":2022,"publication_date":"2022-08-07","ids":{"openalex":"https://openalex.org/W4292873301","doi":"https://doi.org/10.1109/mwscas54063.2022.9859268"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas54063.2022.9859268","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas54063.2022.9859268","pdf_url":null,"source":{"id":"https://openalex.org/S4363606568","display_name":"2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065990002","display_name":"Soniya Chittoriya","orcid":null},"institutions":[{"id":"https://openalex.org/I119241673","display_name":"Indian Institute of Technology Ropar","ror":"https://ror.org/02qkhhn56","country_code":"IN","type":"education","lineage":["https://openalex.org/I119241673"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Soniya Chittoriya","raw_affiliation_strings":["Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001","institution_ids":["https://openalex.org/I119241673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063603115","display_name":"Shivdeep Shivdeep","orcid":null},"institutions":[{"id":"https://openalex.org/I119241673","display_name":"Indian Institute of Technology Ropar","ror":"https://ror.org/02qkhhn56","country_code":"IN","type":"education","lineage":["https://openalex.org/I119241673"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shivdeep","raw_affiliation_strings":["Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001","institution_ids":["https://openalex.org/I119241673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035677304","display_name":"Kundan Kumar Jha","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kundan Kumar Jha","raw_affiliation_strings":["Intel Technology India Pvt Ltd,Bangalore,India,560103"],"affiliations":[{"raw_affiliation_string":"Intel Technology India Pvt Ltd,Bangalore,India,560103","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038798963","display_name":"Devarshi Mrinal Das","orcid":"https://orcid.org/0000-0002-8092-0979"},"institutions":[{"id":"https://openalex.org/I119241673","display_name":"Indian Institute of Technology Ropar","ror":"https://ror.org/02qkhhn56","country_code":"IN","type":"education","lineage":["https://openalex.org/I119241673"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Devarshi Mrinal Das","raw_affiliation_strings":["Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001","institution_ids":["https://openalex.org/I119241673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020173536","display_name":"Rohit Sharma","orcid":"https://orcid.org/0000-0002-7795-7551"},"institutions":[{"id":"https://openalex.org/I119241673","display_name":"Indian Institute of Technology Ropar","ror":"https://ror.org/02qkhhn56","country_code":"IN","type":"education","lineage":["https://openalex.org/I119241673"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rohit Sharma","raw_affiliation_strings":["Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Ropar,Department of Electrical Engineering,Rupnagar,Punjab,140001","institution_ids":["https://openalex.org/I119241673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5065990002"],"corresponding_institution_ids":["https://openalex.org/I119241673"],"apc_list":null,"apc_paid":null,"fwci":0.4288,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.47017189,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7334191799163818},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6428941488265991},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6371315717697144},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6128010749816895},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.5247029066085815},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.41855114698410034},{"id":"https://openalex.org/keywords/physical-unclonable-function","display_name":"Physical unclonable function","score":0.41078490018844604},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40267378091812134},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.40010759234428406},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2340477705001831},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21050438284873962},{"id":"https://openalex.org/keywords/arbiter","display_name":"Arbiter","score":0.14741837978363037},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.10094434022903442}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7334191799163818},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6428941488265991},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6371315717697144},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6128010749816895},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.5247029066085815},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.41855114698410034},{"id":"https://openalex.org/C8643368","wikidata":"https://www.wikidata.org/wiki/Q4046262","display_name":"Physical unclonable function","level":3,"score":0.41078490018844604},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40267378091812134},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.40010759234428406},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2340477705001831},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21050438284873962},{"id":"https://openalex.org/C2779971761","wikidata":"https://www.wikidata.org/wiki/Q629872","display_name":"Arbiter","level":2,"score":0.14741837978363037},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.10094434022903442},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas54063.2022.9859268","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas54063.2022.9859268","pdf_url":null,"source":{"id":"https://openalex.org/S4363606568","display_name":"2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1975641979","https://openalex.org/W2067008732","https://openalex.org/W2103468612","https://openalex.org/W2789948605","https://openalex.org/W2921578610","https://openalex.org/W2953588968","https://openalex.org/W2971591205","https://openalex.org/W2973749287","https://openalex.org/W3086687520","https://openalex.org/W3092370864","https://openalex.org/W3107790108","https://openalex.org/W3135042431","https://openalex.org/W3147830305"],"related_works":["https://openalex.org/W2001654810","https://openalex.org/W1852363244","https://openalex.org/W2078827749","https://openalex.org/W4213238657","https://openalex.org/W3086687520","https://openalex.org/W2046161690","https://openalex.org/W4292873301","https://openalex.org/W2569480541","https://openalex.org/W2002185056","https://openalex.org/W2153702200"],"abstract_inverted_index":{"A":[0,61],"PUF":[1,62],"based":[2,63],"hardware":[3],"security":[4],"circuit":[5,101],"(PBHSC)":[6],"is":[7,108,124,147],"proposed":[8,46,88,106,122],"for":[9,14],"testable":[10],"ICs":[11],"containing":[12],"design":[13,123,134],"testability":[15],"(DFT)":[16],"circuitry.":[17,60],"DFT":[18,52,113],"techniques":[19],"such":[20,39,115],"as":[21,40,92,116],"scan":[22],"chain":[23],"enhance":[24],"the":[25,76,84,87,97,100,111],"controllability":[26],"and":[27,65,79,83,132,152],"observability":[28],"of":[29,32,58,75,86,96,99],"internal":[30],"nodes":[31],"an":[33],"IC,":[34],"which":[35],"leads":[36],"to":[37,51,149],"vulnerabilities":[38],"IP":[41],"theft":[42],"or":[43],"tampering.":[44],"The":[45,105,121],"solution":[47],"restricts":[48],"unauthorized":[49],"access":[50],"structures":[53],"by":[54],"inhibiting":[55],"enable":[56,68],"pin":[57],"test":[59,69,103],"lock":[64],"key":[66],"mechanism":[67],"circuitry":[70],"only":[71],"upon":[72],"successful":[73],"authentication":[74],"user.":[77],"Area":[78],"power":[80,155],"consumption":[81],"overheads":[82],"latency":[85],"technique":[89,107],"are":[90,94],"insignificant":[91],"these":[93],"independent":[95],"size":[98],"under":[102],"(CUT).":[104],"compatible":[109],"with":[110],"industry-standard":[112],"architectures":[114],"scan-chain,":[117],"BIST,":[118],"JTAG,":[119],"etc.":[120],"implemented":[125],"on":[126],"Zynq":[127],"UltraScale":[128],"+":[129],"ZCU102":[130],"FPGA":[131],"Vivado":[133],"suite.":[135],"Proposed":[136],"PBHSC":[137],"utilizes":[138],"11":[139],"LUTs,":[140],"7":[141],"registers,":[142],"1":[143,145],"clock-buffer,":[144],"clock-cycle":[146],"used":[148],"produce":[150],"output,":[151],"consumes":[153],"18mW":[154],"at":[156],"100MHz.":[157]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}