{"id":"https://openalex.org/W3083615186","doi":"https://doi.org/10.1109/mwscas48704.2020.9184563","title":"An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks","display_name":"An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks","publication_year":2020,"publication_date":"2020-08-01","ids":{"openalex":"https://openalex.org/W3083615186","doi":"https://doi.org/10.1109/mwscas48704.2020.9184563","mag":"3083615186"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas48704.2020.9184563","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas48704.2020.9184563","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031863054","display_name":"John M. Emmert","orcid":"https://orcid.org/0000-0002-6074-535X"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John M. Emmert","raw_affiliation_strings":["Dept. of EECS, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of EECS, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026889437","display_name":"Anvesh Perumalla","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anvesh Perumalla","raw_affiliation_strings":["Dept. of EECS, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of EECS, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017567806","display_name":"L. Concha","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luis Concha","raw_affiliation_strings":["Dept. of EECS, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of EECS, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63135867"],"apc_list":null,"apc_paid":null,"fwci":0.23,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.49188976,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"840","last_page":"843"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7112424969673157},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6990752816200256},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6857978105545044},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5910523533821106},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.542097806930542},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5403561592102051},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5123418569564819},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4885898232460022},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.46672073006629944},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4571118652820587},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4405444860458374},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4396190643310547},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.43458104133605957},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4205556809902191},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.396896094083786},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3396487832069397},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.2207442820072174},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1835080087184906},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1737581491470337},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17067167162895203},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.12196937203407288},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.12161988019943237}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7112424969673157},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6990752816200256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6857978105545044},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5910523533821106},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.542097806930542},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5403561592102051},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5123418569564819},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4885898232460022},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.46672073006629944},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4571118652820587},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4405444860458374},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4396190643310547},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.43458104133605957},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4205556809902191},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.396896094083786},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3396487832069397},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.2207442820072174},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1835080087184906},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1737581491470337},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17067167162895203},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.12196937203407288},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.12161988019943237},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas48704.2020.9184563","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas48704.2020.9184563","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6000000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1504392714","https://openalex.org/W2097624522","https://openalex.org/W2099664430","https://openalex.org/W2117299791","https://openalex.org/W2154909745","https://openalex.org/W2161998562","https://openalex.org/W3015979471","https://openalex.org/W6682554491"],"related_works":["https://openalex.org/W3013792460","https://openalex.org/W3117015220","https://openalex.org/W1528933814","https://openalex.org/W1904803855","https://openalex.org/W2014165129","https://openalex.org/W3022525969","https://openalex.org/W2466591189","https://openalex.org/W2525933112","https://openalex.org/W2170504327","https://openalex.org/W2526300902"],"abstract_inverted_index":{"One":[0],"approach":[1],"to":[2,8,60,75,100,109,160],"mitigate":[3],"side-channel":[4],"attacks":[5],"(SCAs)":[6],"is":[7,196],"use":[9],"clockless,":[10,204],"asynchronous":[11,22,89,139,205],"digital":[12,63],"logic.":[13],"To":[14,65],"simplify":[15],"this":[16],"process,":[17],"we":[18,69],"propose":[19],"a":[20,26,33,37,44,77,135,143,174,183,203],"unique":[21,126],"FPGA":[23,95,156],"based":[24],"on":[25],"new":[27],"THx2":[28,79,104,130,194],"programmable":[29,38,57,78,129],"threshold":[30,80,105,140],"cell.":[31],"At":[32],"minimum,":[34],"FPGAs":[35],"require":[36],"logic":[39,48,149],"cell":[40,81,96,120,195],"that":[41,50,67],"can":[42,52],"implement":[43,76,101],"complete":[45,92,136,144],"set":[46,137,145],"of":[47,72,83,134,138,146,154,163],"so":[49],"it":[51,171],"be":[53,191],"connected":[54],"through":[55],"the":[56,102,112,155,161],"interconnect":[58],"network":[59],"form":[61],"any":[62],"system.":[64],"meet":[66],"criteria,":[68],"take":[70],"advantage":[71],"CMOS":[73],"transistors":[74,99,108,121,164],"capable":[82],"performing":[84],"both":[85],"TH12":[86,113],"and":[87,114,117,142,167,199],"TH22":[88,115],"operations.":[90],"Our":[91,125],"sixteen":[93],"transistor":[94,180],"includes":[97],"eight":[98,168],"base":[103],"operation,":[106],"three":[107],"switch":[110],"between":[111],"modes,":[116],"five":[118],"memory":[119],"for":[122,173,201],"mode":[123],"storage.":[124],"minimal":[127],"transistor,":[128],"implementation":[131],"enables":[132],"formation":[133],"gates":[141],"standard":[147],"combinational":[148],"functions.":[150],"The":[151],"symmetric":[152],"nature":[153],"cell,":[157],"in":[158],"regard":[159],"number":[162],"(eight":[165],"NMOS":[166],"PMOS),":[169],"makes":[170],"ideal":[172],"four":[175,178],"row":[176],"by":[177],"column":[179],"grid":[181],"with":[182],"nearly":[184],"square,":[185],"easily":[186],"array-able":[187],"layout.":[188],"It":[189],"should":[190],"noted":[192],"our":[193],"highly":[197],"compact":[198],"suitable":[200],"implementing":[202],"FPGA.":[206]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}