{"id":"https://openalex.org/W3200424893","doi":"https://doi.org/10.1109/mwscas47672.2021.9531835","title":"A Novel Architecture for Memristor-Based Logic","display_name":"A Novel Architecture for Memristor-Based Logic","publication_year":2021,"publication_date":"2021-08-09","ids":{"openalex":"https://openalex.org/W3200424893","doi":"https://doi.org/10.1109/mwscas47672.2021.9531835","mag":"3200424893"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas47672.2021.9531835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas47672.2021.9531835","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064059133","display_name":"Farzad Mozafari","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Farzad Mozafari","raw_affiliation_strings":["University of Windsor, Windsor, Canada"],"affiliations":[{"raw_affiliation_string":"University of Windsor, Windsor, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060396681","display_name":"Mohammad Javad Sharifi","orcid":"https://orcid.org/0000-0003-4065-0115"},"institutions":[{"id":"https://openalex.org/I48379061","display_name":"Shahid Beheshti University","ror":"https://ror.org/0091vmj44","country_code":"IR","type":"education","lineage":["https://openalex.org/I48379061"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohammad Javad Sharifi","raw_affiliation_strings":["University of Shahid Beheshti, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"University of Shahid Beheshti, Tehran, Iran","institution_ids":["https://openalex.org/I48379061"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100833525","display_name":"Arash Ahmadi","orcid":"https://orcid.org/0000-0001-5094-5967"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Arash Ahmadi","raw_affiliation_strings":["University of Windsor, Windsor, Canada"],"affiliations":[{"raw_affiliation_string":"University of Windsor, Windsor, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5116239815","display_name":"Majid Ahmadi","orcid":"https://orcid.org/0009-0006-4046-2121"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Majid Ahmadi","raw_affiliation_strings":["University of Windsor, Windsor, Canada"],"affiliations":[{"raw_affiliation_string":"University of Windsor, Windsor, Canada","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5064059133"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":0.5014,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.64170685,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"812","last_page":"815"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9940999746322632,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.902119517326355},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.8033900260925293},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7892091274261475},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.7559391856193542},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.7376003265380859},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.7243446111679077},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5831078290939331},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.5664188265800476},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.54430091381073},{"id":"https://openalex.org/keywords/nor-logic","display_name":"NOR logic","score":0.527237594127655},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5114966630935669},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.46285855770111084},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.45386576652526855},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.45107996463775635},{"id":"https://openalex.org/keywords/or-gate","display_name":"OR gate","score":0.43276792764663696},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.42032933235168457},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4119381606578827},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.40358683466911316},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35396212339401245},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.345825731754303},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3450953960418701},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18703418970108032}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.902119517326355},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.8033900260925293},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7892091274261475},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.7559391856193542},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.7376003265380859},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.7243446111679077},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5831078290939331},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.5664188265800476},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.54430091381073},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.527237594127655},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5114966630935669},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.46285855770111084},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.45386576652526855},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.45107996463775635},{"id":"https://openalex.org/C58140894","wikidata":"https://www.wikidata.org/wiki/Q560398","display_name":"OR gate","level":4,"score":0.43276792764663696},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.42032933235168457},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4119381606578827},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.40358683466911316},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35396212339401245},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.345825731754303},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3450953960418701},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18703418970108032}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas47672.2021.9531835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas47672.2021.9531835","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1532559922","https://openalex.org/W2004782555","https://openalex.org/W2025674646","https://openalex.org/W2066280488","https://openalex.org/W2073273918","https://openalex.org/W2081729575","https://openalex.org/W2083537989","https://openalex.org/W2162651880","https://openalex.org/W2342387592","https://openalex.org/W2516467421","https://openalex.org/W2614631111","https://openalex.org/W2793595879","https://openalex.org/W2803392934","https://openalex.org/W2964151426","https://openalex.org/W6631737855"],"related_works":["https://openalex.org/W4252993849","https://openalex.org/W188762367","https://openalex.org/W3200424893","https://openalex.org/W2737682879","https://openalex.org/W2616524835","https://openalex.org/W4246304997","https://openalex.org/W2944454566","https://openalex.org/W2963244787","https://openalex.org/W1963739940","https://openalex.org/W4321519815"],"abstract_inverted_index":{"This":[0],"paper,":[1],"proposes":[2],"a":[3,112],"new":[4],"memristor-based":[5],"NAND/NOR":[6],"logic":[7,17,67,79,124],"gates":[8,18,80,98],"using":[9,91,104],"convert":[10],"Voltage":[11],"to":[12,29,33],"Memristance":[13],"(VTM)":[14],"method.":[15],"Universal":[16],"with":[19,111,134],"similar":[20],"structure":[21,40],"require":[22],"two":[23,43],"different":[24],"input":[25,44],"voltages":[26,64],"in":[27,119],"order":[28],"program":[30],"the":[31,66,75,96,123],"gate":[32],"NAND":[34],"or":[35],"NOR":[36],"functions.":[37],"The":[38],"proposed":[39,100],"consists":[41],"of":[42,69,95,107,122],"terminals":[45],"memristors":[46],"(M":[47,56],"<inf":[48,57,71],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[49,58,72],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">in</inf>":[50],"),":[51],"and":[52,65,86,99,129],"one":[53],"output":[54],"memristor":[55],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">out</inf>":[59,73],").":[60],"Gate":[61],"inputs":[62],"are":[63,102],"value":[68],"M":[70],"is":[74],"output.":[76],"Also,":[77],"other":[78],"such":[81],"as":[82],"NOT,":[83],"AND/OR,":[84],"XOR":[85],"XNOR":[87],"can":[88],"be":[89],"implemented":[90],"this":[92],"approach.":[93],"All":[94],"digital":[97],"circuits":[101],"evaluated":[103],"SPICE":[105],"model":[106],"bipolar":[108],"memristive":[109],"system":[110],"given":[113],"threshold.":[114],"Simulation":[115],"results":[116],"show":[117],"improvement":[118],"operation":[120],"step":[121],"gates,":[125],"higher":[126],"switching":[127],"speed,":[128],"lower":[130],"power":[131],"consumption":[132],"compared":[133],"previous":[135],"works.":[136]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-01-13T01:12:25.745995","created_date":"2025-10-10T00:00:00"}