{"id":"https://openalex.org/W2982624934","doi":"https://doi.org/10.1109/mwscas.2019.8885044","title":"VLSI Architecture Design of 9/7 Discrete Wavelet Transform for Image Processing","display_name":"VLSI Architecture Design of 9/7 Discrete Wavelet Transform for Image Processing","publication_year":2019,"publication_date":"2019-08-01","ids":{"openalex":"https://openalex.org/W2982624934","doi":"https://doi.org/10.1109/mwscas.2019.8885044","mag":"2982624934"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2019.8885044","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2019.8885044","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090253908","display_name":"Sadaf Javed","orcid":null},"institutions":[{"id":"https://openalex.org/I69716792","display_name":"Mirpur University of Science and Technology","ror":"https://ror.org/04qjkhc08","country_code":"PK","type":"education","lineage":["https://openalex.org/I69716792"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Sadaf Javed","raw_affiliation_strings":["Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, AJK, Pakistan","Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, AJK, Pakistan","institution_ids":["https://openalex.org/I69716792"]},{"raw_affiliation_string":"Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, Pakistan","institution_ids":["https://openalex.org/I69716792"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077756047","display_name":"Ch. Jabbar Younis","orcid":null},"institutions":[{"id":"https://openalex.org/I69716792","display_name":"Mirpur University of Science and Technology","ror":"https://ror.org/04qjkhc08","country_code":"PK","type":"education","lineage":["https://openalex.org/I69716792"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Ch. Jabbar Younis","raw_affiliation_strings":["Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, Pakistan","institution_ids":["https://openalex.org/I69716792"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091552666","display_name":"Mehboob Alam","orcid":"https://orcid.org/0000-0002-2092-4847"},"institutions":[{"id":"https://openalex.org/I69716792","display_name":"Mirpur University of Science and Technology","ror":"https://ror.org/04qjkhc08","country_code":"PK","type":"education","lineage":["https://openalex.org/I69716792"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Mehboob Alam","raw_affiliation_strings":["Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, AJK, Pakistan","Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, AJK, Pakistan","institution_ids":["https://openalex.org/I69716792"]},{"raw_affiliation_string":"Department of Electrical Engineering, Mirpur University of Science and Technology, Mirpur, Pakistan","institution_ids":["https://openalex.org/I69716792"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057380866","display_name":"Yehia Massoud","orcid":"https://orcid.org/0000-0002-6701-0639"},"institutions":[{"id":"https://openalex.org/I108468826","display_name":"Stevens Institute of Technology","ror":"https://ror.org/02z43xh36","country_code":"US","type":"education","lineage":["https://openalex.org/I108468826"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yehia Massoud","raw_affiliation_strings":["School of Systems and Enterprises, Stevens Institute of Technology, Hoboken, NJ, USA","School of Systems and Enterprises, Stevens Institute of Technology, Hoboken, NJ, United States"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Systems and Enterprises, Stevens Institute of Technology, Hoboken, NJ, USA","institution_ids":["https://openalex.org/I108468826"]},{"raw_affiliation_string":"School of Systems and Enterprises, Stevens Institute of Technology, Hoboken, NJ, United States","institution_ids":["https://openalex.org/I108468826"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0915,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.37404756,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"686","last_page":"689"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7227497100830078},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6840169429779053},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6766726970672607},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6277751922607422},{"id":"https://openalex.org/keywords/discrete-wavelet-transform","display_name":"Discrete wavelet transform","score":0.5633312463760376},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5340747833251953},{"id":"https://openalex.org/keywords/jpeg-2000","display_name":"JPEG 2000","score":0.4993131160736084},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4818595349788666},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4583420753479004},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4455382525920868},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.44271978735923767},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.42707139253616333},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4237653911113739},{"id":"https://openalex.org/keywords/image-compression","display_name":"Image compression","score":0.4102114140987396},{"id":"https://openalex.org/keywords/wavelet-transform","display_name":"Wavelet transform","score":0.4094066619873047},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4009575843811035},{"id":"https://openalex.org/keywords/wavelet","display_name":"Wavelet","score":0.3647727072238922},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29116445779800415},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.18642503023147583},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1842363178730011},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.16721943020820618},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.08953976631164551},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08810275793075562}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7227497100830078},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6840169429779053},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6766726970672607},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6277751922607422},{"id":"https://openalex.org/C46286280","wikidata":"https://www.wikidata.org/wiki/Q2414958","display_name":"Discrete wavelet transform","level":4,"score":0.5633312463760376},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5340747833251953},{"id":"https://openalex.org/C69216139","wikidata":"https://www.wikidata.org/wiki/Q931783","display_name":"JPEG 2000","level":5,"score":0.4993131160736084},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4818595349788666},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4583420753479004},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4455382525920868},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.44271978735923767},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.42707139253616333},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4237653911113739},{"id":"https://openalex.org/C13481523","wikidata":"https://www.wikidata.org/wiki/Q412438","display_name":"Image compression","level":4,"score":0.4102114140987396},{"id":"https://openalex.org/C196216189","wikidata":"https://www.wikidata.org/wiki/Q2867","display_name":"Wavelet transform","level":3,"score":0.4094066619873047},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4009575843811035},{"id":"https://openalex.org/C47432892","wikidata":"https://www.wikidata.org/wiki/Q831390","display_name":"Wavelet","level":2,"score":0.3647727072238922},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29116445779800415},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.18642503023147583},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1842363178730011},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.16721943020820618},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.08953976631164551},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08810275793075562},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2019.8885044","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2019.8885044","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W942388176","https://openalex.org/W2028773518","https://openalex.org/W2050380627","https://openalex.org/W2089154377","https://openalex.org/W2091831372","https://openalex.org/W2100231395","https://openalex.org/W2105240746","https://openalex.org/W2105635940","https://openalex.org/W2112704250","https://openalex.org/W2113134211","https://openalex.org/W2118260076","https://openalex.org/W2118408873","https://openalex.org/W2130260887","https://openalex.org/W2131196771","https://openalex.org/W2131256658","https://openalex.org/W2132984323","https://openalex.org/W2144774282","https://openalex.org/W2148642242","https://openalex.org/W2155643628","https://openalex.org/W2159330547","https://openalex.org/W2168758532","https://openalex.org/W2257969604","https://openalex.org/W2921137446","https://openalex.org/W4253179834","https://openalex.org/W6624841708","https://openalex.org/W6683638176","https://openalex.org/W6692506563","https://openalex.org/W6760475563","https://openalex.org/W6835056952"],"related_works":["https://openalex.org/W2107240870","https://openalex.org/W2136295006","https://openalex.org/W2165480138","https://openalex.org/W2107517480","https://openalex.org/W2131024837","https://openalex.org/W4231001357","https://openalex.org/W2063218591","https://openalex.org/W4210326786","https://openalex.org/W2117342402","https://openalex.org/W2539742022"],"abstract_inverted_index":{"In":[0,13,57],"image":[1,133],"processing,":[2],"transform":[3],"coding":[4],"de-correlates":[5],"images":[6],"to":[7,42,48,72],"pre-condition":[8],"them":[9],"for":[10,132],"efficient":[11],"compression.":[12],"this":[14],"work,":[15],"we":[16],"propose":[17],"VLSI":[18],"architecture":[19,30,71,88,98],"design":[20],"of":[21,33,52,87,112],"a":[22,81,116,124,129],"hardware-efficient":[23,125],"9/7":[24,113],"Discrete":[25],"Wavelet":[26],"Transform":[27],"(DWT).":[28],"The":[29,78,96,121],"takes":[31],"advantage":[32],"Canonical":[34],"Signed":[35],"Digit":[36],"(CSD)":[37],"and":[38,44,54,66,134],"Distributed":[39],"Arithmetic":[40],"(DA)":[41],"represent":[43],"optimally":[45],"distribute":[46],"co-efficients":[47],"reduce":[49,73],"the":[50,59,64,70,74],"number":[51],"adder":[53],"shift":[55],"registers.":[56],"addition,":[58],"co-efficient":[60],"multiplication":[61],"also":[62],"exploits":[63],"horizontal":[65],"vertical":[67],"redundancy":[68],"in":[69,119],"hardware":[75,85],"computational":[76],"complexity.":[77],"result":[79,122],"is":[80,99,123],"filter-based":[82],"design,":[83],"exploiting":[84],"path":[86],"using":[89,101],"CSD":[90],"coefficients,":[91],"which":[92,127],"finds":[93],"minimum":[94],"realization.":[95],"proposed":[97],"simulated":[100],"Verilog":[102],"Hardware":[103],"Description":[104],"Language":[105],"(HDL).":[106],"A":[107],"comparison":[108],"with":[109],"other":[110],"architectures":[111],"DWT":[114],"shows":[115],"18.75%":[117],"reduction":[118],"hardware.":[120],"architecture,":[126],"provides":[128],"low-power":[130],"solution":[131],"signal":[135],"processing":[136],"applications.":[137]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}