{"id":"https://openalex.org/W2890506436","doi":"https://doi.org/10.1109/mwscas.2018.8624012","title":"On the Functional Verification of Dynamic Partial Reconfiguration","display_name":"On the Functional Verification of Dynamic Partial Reconfiguration","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W2890506436","doi":"https://doi.org/10.1109/mwscas.2018.8624012","mag":"2890506436"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2018.8624012","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8624012","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089926026","display_name":"Islam Ahmed","orcid":"https://orcid.org/0009-0009-0223-5149"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":true,"raw_author_name":"Islam Ahmed","raw_affiliation_strings":["IC Verification Solutions, Mentor Graphics, a Siemens Business, Cairo, Egypt"],"affiliations":[{"raw_affiliation_string":"IC Verification Solutions, Mentor Graphics, a Siemens Business, Cairo, Egypt","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063929219","display_name":"Hassan Mostafa","orcid":"https://orcid.org/0000-0003-0043-5007"},"institutions":[{"id":"https://openalex.org/I145487455","display_name":"Cairo University","ror":"https://ror.org/03q21mh05","country_code":"EG","type":"education","lineage":["https://openalex.org/I145487455"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Hassan Mostafa","raw_affiliation_strings":["Electronics and Communications Engineering Department, Cairo University, Giza, Egypt"],"affiliations":[{"raw_affiliation_string":"Electronics and Communications Engineering Department, Cairo University, Giza, Egypt","institution_ids":["https://openalex.org/I145487455"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012834813","display_name":"Ahmed N. Mohieldin","orcid":"https://orcid.org/0000-0001-7500-4514"},"institutions":[{"id":"https://openalex.org/I145487455","display_name":"Cairo University","ror":"https://ror.org/03q21mh05","country_code":"EG","type":"education","lineage":["https://openalex.org/I145487455"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Ahmed Nader Mohieldin","raw_affiliation_strings":["Electronics and Communications Engineering Department, Cairo University, Giza, Egypt"],"affiliations":[{"raw_affiliation_string":"Electronics and Communications Engineering Department, Cairo University, Giza, Egypt","institution_ids":["https://openalex.org/I145487455"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5089926026"],"corresponding_institution_ids":["https://openalex.org/I105695857"],"apc_list":null,"apc_paid":null,"fwci":0.2632,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52760023,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2016 1","issue":null,"first_page":"1126","last_page":"1129"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8697583675384521},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7761202454566956},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7731568217277527},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7293575406074524},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6153926253318787},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5224548578262329},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.49948692321777344},{"id":"https://openalex.org/keywords/assertion","display_name":"Assertion","score":0.4724750220775604},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4681297540664673},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4655868113040924},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3673769235610962},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.20153221487998962}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8697583675384521},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7761202454566956},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7731568217277527},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7293575406074524},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6153926253318787},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5224548578262329},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.49948692321777344},{"id":"https://openalex.org/C40422974","wikidata":"https://www.wikidata.org/wiki/Q741248","display_name":"Assertion","level":2,"score":0.4724750220775604},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4681297540664673},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4655868113040924},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3673769235610962},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.20153221487998962}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mwscas.2018.8624012","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8624012","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.kaust.edu.sa:10754/679456","is_oa":false,"landing_page_url":"http://hdl.handle.net/10754/679456","pdf_url":null,"source":{"id":"https://openalex.org/S4306401596","display_name":"King Abdullah University of Science and Technology Repository (King Abdullah University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I71920554","host_organization_name":"King Abdullah University of Science and Technology","host_organization_lineage":["https://openalex.org/I71920554"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321148","display_name":"Cairo University","ror":"https://ror.org/03q21mh05"},{"id":"https://openalex.org/F4320326598","display_name":"Zewail City of Science and Technology","ror":"https://ror.org/04w5f4y88"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1497207433","https://openalex.org/W1969875970","https://openalex.org/W1980377171","https://openalex.org/W2096001533","https://openalex.org/W2104491791","https://openalex.org/W2158265605","https://openalex.org/W2182586325","https://openalex.org/W2309464846","https://openalex.org/W2585821329","https://openalex.org/W2621963703","https://openalex.org/W2759209791","https://openalex.org/W2772153640","https://openalex.org/W2806977884","https://openalex.org/W2891465786","https://openalex.org/W3144225254","https://openalex.org/W4285719527","https://openalex.org/W6685767205","https://openalex.org/W6698260043"],"related_works":["https://openalex.org/W617996372","https://openalex.org/W2385677473","https://openalex.org/W2382023983","https://openalex.org/W2182055894","https://openalex.org/W2105593427","https://openalex.org/W3120172095","https://openalex.org/W2118572231","https://openalex.org/W1984559585","https://openalex.org/W2106507440","https://openalex.org/W313395762"],"abstract_inverted_index":{"Dynamic":[0],"Partial":[1],"Reconfiguration":[2],"(DPR)":[3],"on":[4,98,166],"Field":[5],"Programmable":[6],"Gate":[7],"Arrays":[8],"(FPGAs)":[9],"allows":[10,29],"reconfiguration":[11,60],"of":[12,14,22,58,75,86,110,126,158],"some":[13],"the":[15,20,23,30,55,59,63,73,84,87,93,99,108,111,124,127,136,139,145,156,159],"logic":[16,24,61],"at":[17],"runtime":[18],"while":[19],"rest":[21],"keeps":[25],"operating.":[26],"This":[27,101],"feature":[28],"designers":[31],"to":[32,53,72,106,121,152],"build":[33],"complex":[34],"systems":[35],"such":[36,78],"as":[37,79],"Software":[38],"Defined":[39],"Radio":[40],"(SDR)":[41],"in":[42],"a":[43,104,167],"reasonable":[44],"area.":[45],"However,":[46],"utilizing":[47],"DPR":[48,76,172],"needs":[49],"more":[50],"verification":[51,150],"efforts":[52],"ensure":[54],"correct":[56],"operation":[57],"and":[62,142],"design":[64,137,147,169],"functionality.":[65],"New":[66],"scenarios":[67],"should":[68],"be":[69],"covered":[70],"due":[71],"usage":[74],"technique":[77,105,163],"guaranteeing":[80],"proper":[81],"connections":[82,109,125],"for":[83],"ports":[85],"Reconfigurable":[88,95],"Modules":[89],"(RMs)":[90],"which":[91],"share":[92],"same":[94],"Region":[96],"(RR)":[97],"FPGA.":[100],"paper":[102],"proposes":[103],"verify":[107,144],"RMs":[112,128],"using":[113,129,148],"Assertion":[114],"Based":[115],"Verification":[116],"(ABV).":[117],"The":[118,161],"proposal":[119],"is":[120,164],"first":[122],"model":[123],"System":[130],"Verilog":[131],"Assertions":[132],"(SVAs),":[133],"then":[134,143],"instrument":[135],"with":[138],"generated":[140],"assertions,":[141],"instrumented":[146],"formal":[149],"methods":[151],"prove":[153],"or":[154],"disprove":[155],"correctness":[157],"connections.":[160],"proposed":[162],"demonstrated":[165],"real":[168],"that":[170],"utilizes":[171],"technique.":[173]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
