{"id":"https://openalex.org/W2913621621","doi":"https://doi.org/10.1109/mwscas.2018.8623984","title":"Influence of CMOS CCII Parasitics in Realization of Two-Integrator Band-Pass Filter","display_name":"Influence of CMOS CCII Parasitics in Realization of Two-Integrator Band-Pass Filter","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W2913621621","doi":"https://doi.org/10.1109/mwscas.2018.8623984","mag":"2913621621"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2018.8623984","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623984","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034946927","display_name":"Edi Emanovi\u0107","orcid":"https://orcid.org/0009-0000-0151-2225"},"institutions":[{"id":"https://openalex.org/I181343428","display_name":"University of Zagreb","ror":"https://ror.org/00mv6sv71","country_code":"HR","type":"education","lineage":["https://openalex.org/I181343428"]}],"countries":["HR"],"is_corresponding":false,"raw_author_name":"Edi Emanovic","raw_affiliation_strings":["Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Unska 3, Croatia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Unska 3, Croatia","institution_ids":["https://openalex.org/I181343428"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059350419","display_name":"Dra\u017een Juri\u0161i\u0107","orcid":"https://orcid.org/0000-0002-5263-5249"},"institutions":[{"id":"https://openalex.org/I181343428","display_name":"University of Zagreb","ror":"https://ror.org/00mv6sv71","country_code":"HR","type":"education","lineage":["https://openalex.org/I181343428"]}],"countries":["HR"],"is_corresponding":false,"raw_author_name":"Drazen Jurisic","raw_affiliation_strings":["Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Unska 3, Croatia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Unska 3, Croatia","institution_ids":["https://openalex.org/I181343428"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017200623","display_name":"G.S. Moschytz","orcid":null},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"George S. Moschytz","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat-Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat-Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.223,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.5522824,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"89","last_page":"92"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-biquad-filter","display_name":"Digital biquad filter","score":0.9555867910385132},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7661364674568176},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.6138976812362671},{"id":"https://openalex.org/keywords/realizability","display_name":"Realizability","score":0.5807986259460449},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5803671479225159},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5659353733062744},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.4523925185203552},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.4482189416885376},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.37369367480278015},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.36911875009536743},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.36156660318374634},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2979789972305298},{"id":"https://openalex.org/keywords/low-pass-filter","display_name":"Low-pass filter","score":0.2948701083660126},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22199717164039612},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.18568027019500732},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1279718577861786}],"concepts":[{"id":"https://openalex.org/C14455310","wikidata":"https://www.wikidata.org/wiki/Q5276043","display_name":"Digital biquad filter","level":4,"score":0.9555867910385132},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7661364674568176},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.6138976812362671},{"id":"https://openalex.org/C2776378722","wikidata":"https://www.wikidata.org/wiki/Q3454417","display_name":"Realizability","level":2,"score":0.5807986259460449},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5803671479225159},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5659353733062744},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.4523925185203552},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.4482189416885376},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.37369367480278015},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.36911875009536743},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.36156660318374634},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2979789972305298},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.2948701083660126},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22199717164039612},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.18568027019500732},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1279718577861786},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2018.8623984","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623984","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W342098007","https://openalex.org/W2025200141","https://openalex.org/W2039887683","https://openalex.org/W2069092617","https://openalex.org/W2120190705","https://openalex.org/W2768121811","https://openalex.org/W2770187581","https://openalex.org/W2801705108"],"related_works":["https://openalex.org/W1603488308","https://openalex.org/W4298120007","https://openalex.org/W2136737082","https://openalex.org/W2538593453","https://openalex.org/W2357947109","https://openalex.org/W2124217752","https://openalex.org/W2162104246","https://openalex.org/W2086223105","https://openalex.org/W2113397720","https://openalex.org/W1979000974"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"examine":[4],"the":[5,25,27,32,36,51,61,70,78],"influence":[6],"of":[7,15,24,31,39,80],"CMOS":[8],"CCII":[9,46,62],"non-idealities":[10],"in":[11,69],"an":[12],"IC":[13],"realization":[14],"a":[16,81],"two-integrator":[17],"Biquad.":[18],"We":[19],"compare":[20],"two":[21],"CMOS-CCII":[22],"realizations":[23],"Biquad;":[26],"same":[28],"basic":[29],"topology":[30],"translinear":[33],"CCIIs,":[34],"but":[35],"W/L":[37],"ratios":[38],"their":[40],"transistors":[41],"are":[42,67,75],"optimized":[43],"differently.":[44],"One":[45],"possesses":[47],"fewer":[48],"non-idealities,":[49],"while":[50],"other":[52],"operates":[53],"at":[54],"higher":[55],"frequencies.":[56],"It":[57],"is":[58],"shown":[59],"how":[60],"nonidealities,":[63],"causing":[64],"lossy":[65],"integrators,":[66],"applied":[68],"Biquad":[71],"design.":[72],"Realizability":[73],"constraints":[74],"given.":[76],"With":[77],"example":[79],"fourth-order":[82],"1MHz/100kHz":[83],"BP":[84],"filter,":[85],"post-layout":[86],"simulations":[87],"with":[88,97],"AMS":[89],"0.35-micron":[90],"technology":[91],"using":[92],"Cadence,":[93],"show":[94],"close":[95],"agreement":[96],"our":[98],"analysis.":[99]},"counts_by_year":[{"year":2019,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}