{"id":"https://openalex.org/W2912193188","doi":"https://doi.org/10.1109/mwscas.2018.8623982","title":"A Dual-Path Open-Loop CMOS Slew-Rate Controlled Output Driver with low PVT Variation","display_name":"A Dual-Path Open-Loop CMOS Slew-Rate Controlled Output Driver with low PVT Variation","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W2912193188","doi":"https://doi.org/10.1109/mwscas.2018.8623982","mag":"2912193188"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2018.8623982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027874968","display_name":"Xiaoyan Gui","orcid":"https://orcid.org/0000-0002-4463-6129"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyan Gui","raw_affiliation_strings":["School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","institution_ids":["https://openalex.org/I87445476"]},{"raw_affiliation_string":"School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100399922","display_name":"Kai Li","orcid":"https://orcid.org/0000-0002-6503-870X"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kai Li","raw_affiliation_strings":["School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","institution_ids":["https://openalex.org/I87445476"]},{"raw_affiliation_string":"School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100456936","display_name":"Xiaoli Wang","orcid":"https://orcid.org/0009-0003-5439-5642"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoli Wang","raw_affiliation_strings":["School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","institution_ids":["https://openalex.org/I87445476"]},{"raw_affiliation_string":"School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043300709","display_name":"Li Geng","orcid":"https://orcid.org/0000-0003-4002-9281"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Li Geng","raw_affiliation_strings":["School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi\u2018an Jiaotong University Xi\u2018an, P.R., China","institution_ids":["https://openalex.org/I87445476"]},{"raw_affiliation_string":"School of Microelectronics, Xi'an Jiaotong University Xi'an, P.R., China","institution_ids":["https://openalex.org/I87445476"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I87445476"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"274","last_page":"277"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.8848850131034851},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6897598505020142},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.46996399760246277},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4576839506626129},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.44761428236961365},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.4422927796840668},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.44106540083885193},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4297792315483093},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.3583453893661499},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27696776390075684},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21438172459602356},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1021849513053894}],"concepts":[{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.8848850131034851},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6897598505020142},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.46996399760246277},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4576839506626129},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.44761428236961365},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.4422927796840668},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.44106540083885193},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4297792315483093},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3583453893661499},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27696776390075684},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21438172459602356},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1021849513053894},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2018.8623982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5799999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1561782264","https://openalex.org/W2097357112","https://openalex.org/W2100581498","https://openalex.org/W2150750735","https://openalex.org/W2169676602"],"related_works":["https://openalex.org/W2014419659","https://openalex.org/W2029904754","https://openalex.org/W2075569182","https://openalex.org/W170188723","https://openalex.org/W2115314666","https://openalex.org/W2099162222","https://openalex.org/W1989271320","https://openalex.org/W4285408939","https://openalex.org/W2031160685","https://openalex.org/W2054436653"],"abstract_inverted_index":{"A":[0,29],"dual-path":[1,30],"open-loop":[2,31],"slew-rate":[3,21,60],"controlled":[4],"CMOS":[5,50],"driver":[6,12,55],"is":[7,33],"presented.":[8],"The":[9],"proposed":[10],"output":[11,42,79],"incorporates":[13],"a":[14,77],"delay-locked":[15],"loop":[16],"(DLL)":[17],"to":[18,35,70],"minimize":[19],"the":[20,37,41,46,54],"variation":[22,61],"over":[23,66],"process,":[24],"voltage":[25],"and":[26],"temperature":[27],"(PVT).":[28],"structure":[32],"introduced":[34],"cancel":[36],"high-frequency":[38],"components":[39],"of":[40,76],"signal.":[43],"Simulation":[44],"using":[45],"Global":[47],"Foundry":[48],"0.18\u03bcm":[49],"process":[51],"shows":[52],"that":[53,75],"achieves":[56],"less":[57],"than":[58],"0.66V/ns":[59],"operating":[62],"at":[63],"500":[64],"Mbps":[65],"16":[67],"corners,":[68],"corresponding":[69],"56%":[71],"reduction":[72],"compared":[73],"with":[74],"conventional":[78],"driver.":[80]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
